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  • 1.
    Aasa, Amanda
    et al.
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Svennblad, Amanda
    Linköping University, Department of Electrical Engineering, Integrated Circuits and Systems.
    Design of an Automated Test Setup for Power-Controlled Nerve Stimulator Using NFC for Implantable Sensors2021Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Electrical stimulation on nerves is a relatively new area of research and has been proved to speed up recoveryfrom nerve damage. In this work, the efficiency and stability of antennas integrated on printed circuit boards provided by the department of electrical engineering are examined. An automated test bench containing a stepmotor with a slider and an Arduino is created. Different setups were used when measuring on the boards, which resulted in that the largest antenna gave the most stable output despite the distance between transmitterand receiver. The conclusion was that the second best antenna and the smallest one would be suitable as well,and the better choice if it is to be implemented under the skin. A physical setup consisting of LEDs, an Arduino, a computer, and a function generator was created to examinethe voltage control functionality, where colored LEDs were lit depending on the voltage level. The functionality was then implemented in a circuit that in the future shall be integrated on the printed circuit board. To control high voltages a limiter circuit was examined and implemented. The circuit was simulated and tested, with a realization that a feature covering voltage enlargement is needed for the future. 

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  • 2.
    Abbaneo, Chiara
    et al.
    Ansaldo STS, Italy.
    Flammini, Francesco
    Ansaldo STS, Italy ; University of Naples ”Federico II”, Italy.
    Lazzaro, Armando
    Ansaldo STS, Italy.
    Marmo, Pietro
    Ansaldo STS, Italy.
    Mazzocca, Nicola
    Université “Federico II” di Napoli, Italy.
    Sanseviero, Angela
    Ansaldo STS, Italy.
    UML based reverse engineering for the verification of railway control logics2007In: Proceedings of International Conference on Dependability of Computer Systems, DepCoS-RELCOMEX 2006, IEEE, 2007, p. 3-10Conference paper (Refereed)
    Abstract [en]

    The Unified Modeling Language (UML) is widely used as a high level object oriented specification language. In this paper we present a novel approach in which reverse engineering is performed using UML as the modelling language used to achieve a representation of the implemented system. The target is the core logic of a complex critical railway control system, which was written in an application specific legacy language. UML perfectly suited to represent the nature of the core logic, made up by concurrent and interacting processes, using a bottom-up approach and proper modeling rules. Each process, in fact, was strictly related to the management of a physically (resp. logically) well distinguished railway device (resp. functionality). The obtained model deeply facilitated the static analysis of the logic code, allowing for at a glance verification of correctness and compliance with higher-level specifications, and opened the way to refactoring and other formal analyses. © 2006 IEEE.

  • 3.
    Abbaneo, Chiara
    et al.
    Ansaldo STS, Italy.
    Flammini, Francesco
    Ansaldo STS, Italy ; University of Naples ”Federico II”, Italy.
    Lazzaro, Armando
    Ansaldo STS, Italy.
    Marmo, Pietro
    Ansaldo STS, Italy.
    Mazzocca, Nicola
    Université “Federico II” di Napoli, Italy.
    Sanseviero, Angela
    Ansaldo STS, Italy.
    UML based reverse engineering for the verification of railway control logics2007In: Proceedings of International Conference on Dependability of Computer Systems, DepCoS-RELCOMEX 2006, IEEE , 2007, p. 3-10Conference paper (Refereed)
    Abstract [en]

    The Unified Modeling Language (UML) is widely used as a high level object oriented specification language. In this paper we present a novel approach in which reverse engineering is performed using UML as the modelling language used to achieve a representation of the implemented system. The target is the core logic of a complex critical railway control system, which was written in an application specific legacy language. UML perfectly suited to represent the nature of the core logic, made up by concurrent and interacting processes, using a bottom-up approach and proper modeling rules. Each process, in fact, was strictly related to the management of a physically (resp. logically) well distinguished railway device (resp. functionality). The obtained model deeply facilitated the static analysis of the logic code, allowing for at a glance verification of correctness and compliance with higher-level specifications, and opened the way to refactoring and other formal analyses. © 2006 IEEE.

  • 4.
    Abbas, Muhammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. RISE Research Institutes of Sweden.
    Requirements-Level Reuse Recommendation and Prioritization of Product Line Assets2021Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Software systems often target a variety of different market segments. Targeting varying customer requirements requires a product-focused development process. Software Product Line (SPL) engineering is one possible approach based on reuse rationale to aid quick delivery of quality product variants at scale. SPLs reuse common features across derived products while still providing varying configuration options. The common features, in most cases, are realized by reusable assets. In practice, the assets are reused in a clone-and-own manner to reduce the upfront cost of systematic reuse. Besides, the assets are implemented in increments, and requirements prioritization also has to be done. In this context, the manual reuse analysis and prioritization process become impractical when the number of derived products grows. Besides, the manual reuse analysis process is time-consuming and heavily dependent on the experience of engineers.

    In this licentiate thesis, we study requirements-level reuse recommendation and prioritization for SPL assets in industrial settings. We first identify challenges and opportunities in SPLs where reuse is done in a clone-and-own manner.  We then focus on one of the identified challenges: requirements-based SPL assets reuse and provide automated support for identifying reuse opportunities for SPL assets based on requirements. Finally, we provide automated support for requirements prioritization in the presence of dependencies resulting from reuse.

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  • 5.
    Abbas, Naeem
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Runtime Parallelisation Switching for MPEG4 Encoder on MPSoC2008Independent thesis Advanced level (degree of Master (Two Years)), 80 credits / 120 HE creditsStudent thesis
    Abstract [en]

    The recent development for multimedia applications on mobile terminals raised the need for flexible and scalable computing platforms that are capable of providing considerable (application specific) computational performance within a low cost and a low energy budget. The MPSoC with multi-disciplinary approach, resolving application mapping, platform architecture and runtime management issues, provides such multiple heterogeneous, flexible processing elements. In MPSoC, the run-time manager takes the design time exploration information as an input and selects an active Pareto point based on quality requirement and available platform resources, where a Pareto point corresponds to a particular parallelization possibility of target application. To use system’s scalability at best and enhance application’s flexibility a step further, the resource management and Pareto point selection decisions need to be adjustable at run-time. This thesis work experiments run-time Pareto point switching for MPEG-4 encoder. The work involves design time exploration and then embedding of two parallelization possibilities of MPEG-4 encoder into one single component and enabling run-time switching between parallelizations, to give run-time control over adjusting performance-cost criteria and allocation de-allocation of hardware resources at run-time. The newer system has the capability to encode each video frame with different parallelization. The obtained results offer a number of operating points on Pareto curve in between the previous ones at sequence encoding level. The run-time manager can improve application performance up to 50% or can save memory bandwidth up to 15%, according to quality request.

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  • 6.
    Abbas, Taimoor
    et al.
    Lund Univ, Elect & Informat Technol Dept, S-22100 Lund, Sweden..
    Sjöberg, Katrin
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Kåredal, Johan
    Lund Univ, Elect & Informat Technol Dept, S-22100 Lund, Sweden..
    Tufvesson, Fredrik
    Lund Univ, Elect & Informat Technol Dept, S-22100 Lund, Sweden..
    A Measurement Based Shadow Fading Model for Vehicle-to-Vehicle Network Simulations2015In: International Journal of Antennas and Propagation, ISSN 1687-5869, E-ISSN 1687-5877, article id 190607Article in journal (Refereed)
    Abstract [en]

    The vehicle-to-vehicle (V2V) propagation channel has significant implications on the design and performance of novel communication protocols for vehicular ad hoc networks (VANETs). Extensive research efforts have been made to develop V2V channel models to be implemented in advanced VANET system simulators for performance evaluation. The impact of shadowing caused by other vehicles has, however, largely been neglected in most of the models, as well as in the system simulations. In this paper we present a shadow fading model targeting system simulations based on real measurements performed in urban and highway scenarios. The measurement data is separated into three categories, line-of-sight (LOS), obstructed line-of-sight (OLOS) by vehicles, and non-line-of-sight due to buildings, with the help of video information recorded during the measurements. It is observed that vehicles obstructing the LOS induce an additional average attenuation of about 10 dB in the received signal power. An approach to incorporate the LOS/OLOS model into existing VANET simulators is also provided. Finally, system level VANET simulation results are presented, showing the difference between the LOS/OLOS model and a channel model based on Nakagami-m fading.

  • 7.
    Abbasi, Jasim Aftab
    Umeå University, Faculty of Science and Technology, Department of Applied Physics and Electronics.
    Test of Rapid Control System Development using TargetLink2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The aim of this thesis is to employ and evaluate an evaluation board with the standard microprocessor freescale MPC5554EVB board for implementation of control algorithms which are created in Matlab/Simulink instead of using dSPACE prototyping hardware. The Simulink real-time model shall be compiled to the MPC5554EVB board. TargetLink is a powerful software tool which allows an automatic generation of efficient C code from Simulink and facilitates model-based control design. The goal of this thesis is to learn how to use TargetLink in a control design workflow from model to real code and what are the limitations of a microprocessor platform and to evaluate the capabilities of TargetLink to generate a working code for a generic microprocessor.

  • 8.
    Abbaspour Asadollah, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Concurrency Bugs: Characterization, Debugging and Runtime Verification2018Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Concurrent software has been increasingly adopted in recent years, mainly due to the introduction of multicore platforms. However, concurrency bugs are still difficult to test and debug due to their complex interactions involving multiple threads (or tasks). Typically, real world concurrent software has huge state spaces. Thus, testing techniques and handling of concurrency bugs need to focus on exposing the bugs in this large space. However, existing solutions typically do not provide debugging information to developers (and testers) for understanding the bugs.

    Our work focuses on improving concurrent software reliability via three contributions: 1) An investigation of concurrent software challenges with the aim to help developers (and testers) to better understand concurrency bugs. We propose a classification of concurrency bugs and discuss observable properties of each type of bug. In addition, we identify a number of gaps in the body of knowledge on concurrent software bugs and their debugging. 2) Exploring concurrency related bugs in real-world software with respect to the reproducibility of bugs, severity of their consequence and effort required to fix them. Our findings here is that concurrency bugs are different from other bugs in terms of their fixing time and severity, while they are similar in terms of reproducibility. 3) A model for monitoring concurrency bugs and the implementation and evaluation of a related runtime verification tool to detect the bugs. In general, runtime verification techniques are used to (a) dynamically verify that the observed behaviour matches specified properties and (b) explicitly recognize understandable behaviors in the considered software. Our implemented tool is used to detect concurrency bugs in embedded software and is in its current form tailored for the FreeRTOS operating system. It helps developers and testers to automatically identify concurrency bugs and subsequently helps to reduce their finding and fixing time.

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  • 9.
    Abbaspour Asadollah, Sara
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Sundmark, Daniel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Eldh, S.
    Ericsson AB, Kista, Sweden.
    Hansson, Hans
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    A Runtime Verification Tool for Detecting Concurrency Bugs in FreeRTOS Embedded Software2018In: Proceedings - 17th International Symposium on Parallel and Distributed Computing, ISPDC 2018, Institute of Electrical and Electronics Engineers Inc. , 2018, p. 172-179, article id 8452035Conference paper (Refereed)
    Abstract [en]

    This article presents a runtime verification tool for embedded software executing under the open source real-time operating system FreeRTOS. The tool detects and diagnoses concurrency bugs such as deadlock, starvation, and suspension based-locking. The tool finds concurrency bugs at runtime without debugging and tracing the source code. The tool uses the Tracealyzer tool for logging relevant events. Analysing the logs, our tool can detect the concurrency bugs by applying algorithms for diagnosing each concurrency bug type individually. In this paper, we present the implementation of the tool, as well as its functional architecture, together with illustration of its use. The tool can be used during program testing to gain interesting information about embedded software executions. We present initial results of running the tool on some classical bug examples running on an AVR 32-bit board SAM4S. 

  • 10.
    Abbaspour, Sara
    et al.
    Massachusetts Gen Hosp, Dept Neurol, Boston, MA 02114 USA.;Harvard Med Sch, Div Sleep Med, Boston, MA 02114 USA..
    Naber, Autumn
    Ctr Bion & Pain Res, S-43180 Molndal, Sweden.;Chalmers Univ Technol, Dept Elect Engn, S-41296 Gothenburg, Sweden..
    Ortiz-Catalan, Max
    Ctr Bion & Pain Res, S-43180 Molndal, Sweden.;Chalmers Univ Technol, Dept Elect Engn, S-41296 Gothenburg, Sweden.;Sahlgrens Univ Hosp, Operat Area 3, S-43180 Molndal, Sweden.;Univ Gothenburg, Sahlgrenska Acad, Inst Clin Sci, Dept Orthopaed, S-43180 Molndal, Sweden..
    GholamHosseini, Hamid
    Auckland Univ Technol, Dept Elect & Elect Engn, Auckland 1010, New Zealand..
    Lindén, Maria
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Real-Time and Offline Evaluation of Myoelectric Pattern Recognition for the Decoding of Hand Movements2021In: Sensors, E-ISSN 1424-8220, Vol. 21, no 16, article id 5677Article in journal (Refereed)
    Abstract [en]

    Pattern recognition algorithms have been widely used to map surface electromyographic signals to target movements as a source for prosthetic control. However, most investigations have been conducted offline by performing the analysis on pre-recorded datasets. While real-time data analysis (i.e., classification when new data becomes available, with limits on latency under 200-300 milliseconds) plays an important role in the control of prosthetics, less knowledge has been gained with respect to real-time performance. Recent literature has underscored the differences between offline classification accuracy, the most common performance metric, and the usability of upper limb prostheses. Therefore, a comparative offline and real-time performance analysis between common algorithms had yet to be performed. In this study, we investigated the offline and real-time performance of nine different classification algorithms, decoding ten individual hand and wrist movements. Surface myoelectric signals were recorded from fifteen able-bodied subjects while performing the ten movements. The offline decoding demonstrated that linear discriminant analysis (LDA) and maximum likelihood estimation (MLE) significantly (p < 0.05) outperformed other classifiers, with an average classification accuracy of above 97%. On the other hand, the real-time investigation revealed that, in addition to the LDA and MLE, multilayer perceptron also outperformed the other algorithms and achieved a classification accuracy and completion rate of above 68% and 69%, respectively.

  • 11.
    Abdalla, Osman
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Biomedical Engineering and Health Systems, Health Informatics and Logistics.
    Design and implementation of a signaling system for a novel light-baseed bioprinter: Design och implementering av ett signalsystem för en ny ljusbaserad bioprinter2023Independent thesis Basic level (university diploma), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    A 3D bioprinter employing light-based technology has been designed and constructed in an EU-funded research initiative known as BRIGHTER (Bioprinting by Light-Sheet Lithography). This initiative is a collaborative effort between institutions and companies and aims to develop a technique for efficient and accurate production of engineered tissue.

    Presently, the bioprinter’s function is limited to 2D printing, with the lack of 3D printing capabilities. 

    The problem addressed is the integration of two separate electronic systems within the bioprinter to control the laser beam’s trajectory for 3D printing. The goal of the project is to create functional software and simulation tools to control the hardware modules in a precise and synchronized manner, thereby enabling 3D printing.

    The outcome manifests as a software prototype, which successfully facilitates intercommunication between the two electronic subsystems within the bioprinter, thereby enabling further progress on the bioprinter with 3D printing available. Nevertheless, the prototype requires thorough testing to determine its optimal operational efficiency in terms of timing the movements for the various hardware modules.

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    Bioprinter
  • 12.
    Abdirahman, Khalid
    et al.
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Biomedical Engineering and Health Systems, Health Informatics and Logistics.
    Förnberg, Sebastian
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Biomedical Engineering and Health Systems, Health Informatics and Logistics.
    Styrsystem för solcellsladdade batterier2018Independent thesis Basic level (university diploma), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    The use of solar cells is continuously increasing in Sweden and the powergenerated by the solar cells is usually stored in lead acid batteries. These batterieshave a bad impact on the environment as much energy and environmentallyhazardous materials like lead and sulfuric acid are required to manufacture thesebatteries. Östersjökompaniet AB and many of its customers realize the importanceof sustainable thinking and were interested in knowing if it was possible tomaximize the lifetime of these batteries. During the course of the work, differentmethods of battery charging and discharging were analyzed that could affect thebatteries lifetime and how to take care of them to optimize them. A chargecontroller was used to optimize the charge of the battery. To calculate theremaining state of charge in the battery, the Extended voltmeter method was used.A prototype that was able to charge the batteries optimally, warn when the batterycapacity became too low, and a user-friendly application for battery monitoring wasdesigned. The calculated lifetime of a battery is not an exact science. According tostudies the lifetime of a battery can be doubled if it is c

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    Styrsystem för solcellsladdade batterier
  • 13.
    Adeboye, Taiyelolu
    University of Gävle, Faculty of Engineering and Sustainable Development, Department of Electronics, Mathematics and Natural Sciences.
    Robot Goalkeeper: A robotic goalkeeper based on machine vision and motor control2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This report shows a robust and efficient implementation of a speed-optimized algorithm for object recognition, 3D real world location and tracking in real time. It details a design that was focused on detecting and following objects in flight as applied to a football in motion. An overall goal of the design was to develop a system capable of recognizing an object and its present and near future location while also actuating a robotic arm in response to the motion of the ball in flight.

    The implementation made use of image processing functions in C++, NVIDIA Jetson TX1, Sterolabs’ ZED stereoscopic camera setup in connection to an embedded system controller for the robot arm. The image processing was done with a textured background and the 3D location coordinates were applied to the correction of a Kalman filter model that was used for estimating and predicting the ball location.

    A capture and processing speed of 59.4 frames per second was obtained with good accuracy in depth detection while the ball was well tracked in the tests carried out.

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    Robot Goalkeeoer
  • 14.
    Adesiyun, Adewole
    et al.
    FEHRL, Brussels.
    Erdelean, Isabela
    Austrian Institute of Technology (AIT), Vienna.
    Hedhli, Abdelmename
    IFSTTAR, Marne la Vallée, France.
    Lamb, Martin
    Maple Consulting, Caerphilly, Wales.
    Ponweiser, Wolfgang
    Austrian Institute of Technology (AIT), Vienna.
    Strand, Niklas
    Swedish National Road and Transport Research Institute, Traffic and road users, Driver and vehicle.
    Zofka, Ewa
    Erica Consulting, Warsaw, Poland.
    Overview of connected and automated driving test sites2020In: Proceedings of 8th Transport Research Arena TRA 2020, 2020, p. 7-Conference paper (Refereed)
    Abstract [en]

    Connected and automated vehicles potentially offer solutions to some key challenges for National Road Administrations (NRAs), such as reduction of accidents, increasing network capacity etc. As a result of this potential, both industry and certain national governments are undertaking trials that are mainly focused on technological challenges such as the ability of vehicles to drive safely in “random” situations etc. Far less attention has been paid to questions around the implications for NRAs. The overall aim of the STAPLE project is to provide a comprehensive review of technological and non-technological aspects of the most relevant connected and automated driving test sites in order to understand the impact of these sites on the NRAs’ core business and functions.

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    fulltext
  • 15.
    Adhi, Boma
    et al.
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Cortes, Carlos
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Sozzo, Emanuele Del
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Ueno, Tomohiro
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Tan, Yiyu
    Iwate University, Faculty of Science and Engineering, Japan.
    Kojima, Takuya
    Center for Computational Science (R-CCS), RIKEN, Japan; The University of Tokyo, Graduate School of Information Science and Technology, Japan.
    Podobas, Artur
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
    Sano, Kentaro
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Less for more: reducing intra-cgra connectivity for higher performance and efficiency in hpc2023In: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023, Institute of Electrical and Electronics Engineers (IEEE) , 2023, p. 452-459Conference paper (Refereed)
    Abstract [en]

    Coarse-Grained Reconfigurable Arrays (CGRAs) are a class of reconfigurable architectures that inherit the performance of Domain-specific accelerators and the reconfigurability aspects of Field-Programmable Gate Arrays (FPGAs). Historically, CGRAs have been successfully used to accelerate embedded applications and are now considered to accelerate High-Performance Computing (HPC) applications in future supercomputers. However, embedded systems and supercomputers are two vastly different domains with different applications and constraints, and it is today not fully understood what CGRA design decisions adequately cater to the HPC market. One such unknown design decision is regarding the interconnect that facilitates intra-CGRA communication. Our findings show that even the typical king-style mesh-like topology is often under-utilized with a typical HPC workload, leading to inefficiency. This research aims to explore the provisioning of intra-CGRA interconnect for HPC-oriented workloads and, ultimately, recoup the potential performance and efficiency lost by reducing the interconnect complexity. We proposed several reduced interconnect topologies based on the usage statistic. Then we evaluate the tradeoffs regarding hardware cost, routability of DFGs, and computational throughput.

  • 16.
    Adhi, Boma
    et al.
    RIKEN, Ctr Computat Sci R CCS, Kobe, Hyogo, Japan..
    Cortes, Carlos
    RIKEN, Ctr Computat Sci R CCS, Kobe, Hyogo, Japan..
    Tan, Yiyu
    Iwate Univ, Dept Syst Innovat Engn, Sci & Engn, Morioka, Iwate, Japan..
    Kojima, Takuya
    RIKEN, Ctr Computat Sci R CCS, Kobe, Hyogo, Japan.;Univ Tokyo, Grad Sch Informat Sci & Technol, Tokyo, Japan..
    Podobas, Artur
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
    Sano, Kentaro
    RIKEN, Ctr Computat Sci R CCS, Kobe, Hyogo, Japan..
    The Cost of Flexibility: Embedded versus Discrete Routers in CGRAs for HPC2022In: 2022 IEEE INTERNATIONAL CONFERENCE ON CLUSTER COMPUTING (CLUSTER 2022), Institute of Electrical and Electronics Engineers (IEEE) , 2022, p. 347-356Conference paper (Refereed)
    Abstract [en]

    Coarse-Grained Reconfigurable Arrays (CGRAs) are a class of reconfigurable architectures that inherit the performance and usability properties of Central Processing Units (CPUs) and the reconfigurability aspects of Field-Programmable Gate Arrays (FPGAs). Historically, CGRAs have been successfully used to accelerate embedded applications and are today also being considered to accelerate High-Performance Computing (HPC) applications in future supercomputers. However, embedded systems and supercomputers are two vastly different domains with different applications and constraints, and it is today not fully understood what CGRA design decisions adequately cater to the HPC market. One such unknown design decision is regarding the interconnect that facilitates intra-CGRA communication. Today, intra-CGRA communication comes in two flavors: using routers closely embedded into the compute units or using discrete routers outside the compute units. The former trades flexibility for a reduction in hardware cost, while the latter has greater flexibility but is more resource hungry. In this paper, we aspire to understand which of both designs best suits the CGRA HPC segment. We extend our previous methodology, which consists of both a parameterized CGRA design and an OpenMP-capable compiler, to accommodate both types of routing designs, including verification tests using RTL simulation. Our results show that the discrete router design can facilitate better use of processing elements (PEs) compared to embedded routers and can achieve up to 79.27% reduction in unnecessary PE occupancy for an aggressively unrolled stencil kernel on a 18 x 16 CGRA at a (estimated) hardware resource overhead cost of 6.3x. This reduction in PE occupancy can be used, for example, to exploit instruction-level parallelism (ILP) through even more aggressive unrolling.

  • 17.
    Adhi, Boma
    et al.
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Cortes, Carlos
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Ueno, Tomohiro
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Tan, Yiyu
    Iwate University, Department of Systems Innovation Engineering, Japan.
    Kojima, Takuya
    Graduate School of Information Science and Technology, The University of Tokyo, Japan.
    Podobas, Artur
    KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
    Sano, Kentaro
    Center for Computational Science (R-CCS), RIKEN, Japan.
    Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage2022In: FPT 2022: 21st International Conference on Field-Programmable Technology, Proceedings, Institute of Electrical and Electronics Engineers (IEEE) , 2022Conference paper (Refereed)
    Abstract [en]

    This research aims to explore the tradeoffs between routing flexibility and hardware resource usage, ultimately reducing the resource usage of our CGRA architecture while maintaining compute efficiency. we investigate statistics of connection usages among switch blocks for benchmark DFGs, propose several CGRA architecture with a reduced connection, and evaluate their hardware cost, routability of DFGs, and computational throughput for benchmarks. We found that the topology with horizontal plus diagonal connection saves about 30% of the resource usage while maintaining virtually the same routing flexibility as the full connectivity topology.

  • 18.
    Adhikari, Ayush
    University West, Department of Health Sciences.
    Enhancing Vulnerability Management in Large Organisations through Machine Learning - Based Prioritisation: A Case Study2023Independent thesis Advanced level (degree of Master (One Year)), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    The number of vulnerabilities is increasing daily, and organisations are flooded by vulnerabilities in their IT environment. The increasing number of vulnerabilities in organisations' IT environments presents a significant challenge, requiring effective identification and prioritisation of critical vulnerabilities. Different techniques exist to this date, such as CVSS scoring or Risk-based scoring from solution providers to perform prioritisation of vulnerabilities. However, large industries with extensive assets often face difficulty in managing and fixing a large pool of vulnerabilities, as traditional techniques tend to classify numerous vulnerabilities as high or critical. This study proposes a machine learning model based on the K-means++clustering technique that leverages vulnerability data and asset financial value assessments to find patterns within vulnerability and group the most critical vulnerabilities. Our study successfully determined a group of the most critical vulnerabilities from a sample dataset of vulnerabilities from one of the large organisations. By considering the financial value of assets, our solution demonstrates a more accurate prioritisation, enabling organisations to allocate resources effectively and address the most critical vulnerabilities first. This study enhances vulnerability management practices in large organisations and serves as a foundation for further research and development in vulnerability prioritisation using machine learning techniques

  • 19.
    Adnan Abdu, Jihad
    et al.
    Halmstad University, School of Information Technology.
    Lundström, Philip
    Halmstad University, School of Information Technology.
    Water Quality Device: Testing Through Electronic Measurements2023Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Water is the source of all life, but unfortunately, the water quality is getting only worse due to many factors like overuse, contamination, indifference and even by nature itself. By identifying the problem, we are one step closer to solving the problem, and that is why an intelligent water quality device is required to examine water and detect impurities within it. In this project, we are developing a device that uses an entirely new method to measure water quality. Even though the theory behind the device is very advanced, the device is still primitive in its functions and needs development to increase the usefulness and accuracy of the measurements!

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  • 20.
    Adolfsson, Mattias
    Uppsala University, Disciplinary Domain of Science and Technology, Mathematics and Computer Science, Department of Information Technology.
    Developing a Graphical Application to Control Stepper Motors with Sensorless Load Detection2021Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    For positioning of linear stages in absolute coordinates, there is a general need to find a reference position since the initial one is unknown. This is commonly called homing. To reduce costs and facilitate assembly, homing can be performed without additional sensors, known as sensorless homing. This thesis delves into sensorless homing, specifically with respect to stepper motors, and develops a graphical application for control of them. The commercial technology StallGuard is applied inconjunction with exploration into how it – and sensorless load detectionin general – functions. The resulting graphical application can be used to configure the stepper motors, perform homing using StallGuard, and automatically tune StallGuard to work despite varying conditions. In addition, rudimentary sensorless load detection independent from StallGuard is developed, demonstrating how it could work in practice. Testing shows homing with StallGuard resulting in a position within a ±5μm window in 94% of cases, less than 1/7 the width of an average strand of human hair. Additionally, homing is easily performed with a single button press from the graphical interface, with optional additional configuration available.

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  • 21.
    Adrielsson, Anders
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering.
    Zedboard based platform for condition monitoring and control experiments2018Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    New methods for monitoring the condition of roller element bearings in rotating machinery offer possibilities to reduce repair- and maintenance costs, and reduced use of environmentally harmful lubricants. One such method is sparse representation of vibration signals using matching pursuit with dictionary learning, which so far has been tested on PCs with data from controlled tests. Further testing requires a platform capable of signal processing and control in more realistic experiments. This thesis focuses on the integration of a hybrid CPU-FPGA hardware system with a 16-bit analog-to-digital converter and an oil pump, granting the possibility of collecting real-time data, executing the algorithm in closed loop and supplying lubrication to the machine under test, if need be. The aforementioned algorithm is implemented in a Zynq-7000 System-on-Chip and the analog-to-digital converter as well as the pump motor controller are integrated. This platform enables portable operation of the matching pursuit with dictionary learning in the field under a larger variety of environmental and operational conditions, conditions which might prove difficult to reproduce in a laboratory setup. The platform developed throughout this project can collect data using the analog-to-digital converter and operations can be performed on that data in both the CPU and the FPGA. A test of the system function at a sampling rate of 5 kHz is presented and the input and output are verified to function correctly.

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  • 22.
    Afshar, Sara
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Lock-Based Resource Sharing for Real-Time Multiprocessors2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Embedded systems are widely used in the industry and are typically resource constrained, i.e., resources such as processors, I/O devices, shared buffers or shared memory might be limited in the system. Hence, techniques that can enable an efficient usage of processor bandwidths in such systems are of great importance. Locked-based resource sharing protocols are proposed as a solution to overcome resource limitation by allowing the available resources in the system to be safely shared. In recent years, due to a dramatic enhancement in the functionality of systems, a shift from single-core processors to multi-core processors has become inevitable from an industrial perspective to tackle the raised challenges due to increased system complexity. However, the resource sharing protocols are not fully mature for multi-core processors. The two classical multi-core processor resource sharing protocols, spin-based and suspension-based protocols, although providing mutually exclusive access to resources, can introduce long blocking delays to tasks, which may be unacceptable for many industrial applications. In this thesis we enhance the performance of resource sharing protocols for partitioned scheduling, which is the de-facto scheduling standard for industrial real-time multi-core processor systems such as in AUTOSAR, in terms of timing and memory requirements.

     

    A new scheduling approach uses a resource efficient hybrid approach combining both partitioned and global scheduling where the partitioned scheduling is used to schedule the major number of tasks in the system. In such a scheduling approach applications with critical task sets use partitioned scheduling to achieve higher level of predictability. Then the unused bandwidth on each core that is remained from partitioning is used to schedule less critical task sets using global scheduling to achieve higher system utilization. These scheduling schema however lacks a proper resource sharing protocol since the existing protocols designed for partitioned and global scheduling cannot be directly applied due to the complex hybrid structure of these scheduling frameworks. In this thesis we propose a resource sharing solution for such a complex structure. Further, we provide the blocking bounds incurred to tasks under the proposed protocols and enhance the schedulability analysis, which is an essential requirement for real-time systems, with the provided blocking bounds.

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  • 23.
    Afzal, Wahaj
    Halmstad University, School of Information Technology, Center for Applied Intelligent Systems Research (CAISR).
    A Rule-based approach for detection of spatial object relations in images2023Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Deep learning and Computer vision are becoming a part of everyday objects and machines. Involvement of artificial intelligence in human’s daily life open doors to new opportunities and research. This involvement provides the idea of improving upon the in-hand research of spatial relations and coming up with a more generic and robust algorithm that provides us with 2-D and 3-D spatial relations and uses RGB and RGB-D images which can help us with few complex relations such as ‘on’ or ‘in’ as well. Suggested methods are tested on the dataset with animated and real objects, where the number of objects varies in every image from at least 4 to at most 10 objects. The size and orientation of objects are also different in every image.  

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  • 24.
    Agha Jafari Wolde, Bahareh
    Mälardalen University, School of Innovation, Design and Engineering.
    A systematic Mapping study of ADAS and Autonomous Driving2019Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Nowadays, autonomous driving revolution is getting closer to reality. To achieve the Autonomous driving the first step is to develop the Advanced Driver Assistance System (ADAS). Driver-assistance systems are one of the fastest-growing segments in automotive electronics since already there are many forms of ADAS available. To investigate state of art of development of ADAS towards Autonomous Driving, we develop Systematic Mapping Study (SMS). SMS methodology is used to collect, classify, and analyze the relevant publications. A classification is introduced based on the developments carried out in ADAS towards Autonomous driving. According to SMS methodology, we identified 894 relevant publications about ADAS and its developmental journey toward Autonomous Driving completed from 2012 to 2016. We classify the area of our research under three classifications: technical classifications, research types and research contributions. The related publications are classified under thirty-three technical classifications. This thesis sheds light on a better understanding of the achievements and shortcomings in this area. By evaluating collected results, we answer our seven research questions. The result specifies that most of the publications belong to the Models and Solution Proposal from the research type and contribution. The least number of the publications belong to the Automated…Autonomous driving from the technical classification which indicated the lack of publications in this area. 

  • 25.
    Ahlberg, Carl
    et al.
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Leon, Miguel
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ekstrand, Fredrik
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    Ekström, Mikael
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems.
    The Genetic Algorithm Census TransformManuscript (preprint) (Other academic)
  • 26.
    Ahlbäck, Joel
    et al.
    Halmstad University, School of Information Technology.
    Jalking, Jesper
    Halmstad University, School of Information Technology.
    Logistikföretag i försörjningskedjan: Rekommendationer till logistikföretag i hanteringen av informationssäkerhet2021Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Information security is an important aspect when running a business. Before, information security has been separated to the business area of IT. But lately this issue has broadened and become an important part of business-activity. This has resulted in a growing interest among business leaders. Literature within the subject information security mainly focuses on how organizations maintain safe systems and protect themselves from cyber-attacks and information infringements. Existing literature identifies new security threats that have emerged after advances in internet technology, but little is known about how these threats can be managed. Researchers request research on how cooperation in supply chains poses risks to secure information management. Logistics companies provide customers with logistics services such as warehouse management, transport, order processing and packaging. Logistics companies are a central node in supply chains. They often participate in several supply chains in different industries. The extensive interconnection of companies poses a security risk. It also means that logistics companies can be seen as targets for cyber-attacks. The purpose of the study has therefore been to create an understanding of the challenges logistics companies face in managing information security in the supply chain.

     

    The research question has been answered by interviewing representatives from logistics organizations. The empirical data has undergone a thematic analysis. The results of the study show that the management of information security varies between companies. The study’s conclusions present recommendations. The recommendations describe how logistics companies can manage information security in the supply chain.

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  • 27.
    Ahlzén, Anton
    et al.
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Materials Science and Engineering.
    Holma, Ville
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Materials Science and Engineering.
    Segerberg, Adam
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Materials Science and Engineering.
    Varahram, Sam
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Materials Science and Engineering.
    Wiig, Marcus
    Uppsala University, Disciplinary Domain of Science and Technology, Technology, Department of Materials Science and Engineering.
    Piano Hero: Interactive musical learning2024Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Learning to play the piano usually involves learning to read sheet music and many hours of prac- tice, which can be seen as a tough task for beginners. This project presents an innovative ap- proach to piano learning by integrating a Raspberry Pi, Arduino, and LED lights with a Casio CTK-550 keyboard. This system interprets MusicXML files and visually guides users by lighting up the keys they need to press in the correct order, providing a more intuitive and engaging learn- ing experience. Additionally, it has a playback mode that makes the piano play the chosen song while illuminating the keys played. This allows the user to hear the song being played correctly before using the interactive mode to play the entire song themselves. These modifications to the piano aim to simplify the learning process and ease in new piano players by removing the big initial barrier of understanding sheet music. The project practices sustainability by reusing components from old projects and also follows several UN Sustainable Development Goals. After a few iter- ations, there was a product able to fulfill the goals set in advance. Future improvements could include improved lighting precision, additional learning modes, and more user-friendly file transfer possibilities.

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  • 28.
    Ahmad, Naeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Modelling and optimization of sky surveillance visual sensor network2012Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    A Visual Sensor Network (VSN) is a distributed system of a largenumber of camera sensor nodes. The main components of a camera sensornode are image sensor, embedded processor, wireless transceiver and energysupply. The major difference between a VSN and an ordinary sensor networkis that a VSN generates two dimensional data in the form of an image, whichcan be exploited in many useful applications. Some of the potentialapplication examples of VSNs include environment monitoring, surveillance,structural monitoring, traffic monitoring, and industrial automation.However, the VSNs also raise new challenges. They generate large amount ofdata which require higher processing powers, large bandwidth requirementsand more energy resources but the main constraint is that the VSN nodes arelimited in these resources.This research focuses on the development of a VSN model to track thelarge birds such as Golden Eagle in the sky. The model explores a number ofcamera sensors along with optics such as lens of suitable focal length whichensures a minimum required resolution of a bird, flying at the highestaltitude. The combination of a camera sensor and a lens formulate amonitoring node. The camera node model is used to optimize the placementof the nodes for full coverage of a given area above a required lower altitude.The model also presents the solution to minimize the cost (number of sensornodes) to fully cover a given area between the two required extremes, higherand lower altitudes, in terms of camera sensor, lens focal length, camera nodeplacement and actual number of nodes for sky surveillance.The area covered by a VSN can be increased by increasing the highermonitoring altitude and/or decreasing the lower monitoring altitude.However, it also increases the cost of the VSN. The desirable objective is toincrease the covered area but decrease the cost. This objective is achieved byusing optimization techniques to design a heterogeneous VSN. The core ideais to divide a given monitoring range of altitudes into a number of sub-rangesof altitudes. The sub-ranges of monitoring altitudes are covered by individualsub VSNs, the VSN1 covers the lower sub-range of altitudes, the VSN2 coversthe next higher sub-range of altitudes and so on, such that a minimum cost isused to monitor a given area.To verify the concepts, developed to design the VSN model, and theoptimization techniques to decrease the VSN cost, the measurements areperformed with actual cameras and optics. The laptop machines are used withthe camera nodes as data storage and analysis platforms. The area coverage ismeasured at the desired lower altitude limits of homogeneous as well asheterogeneous VSNs and verified for 100% coverage. Similarly, the minimumresolution is measured at the desired higher altitude limits of homogeneous aswell as heterogeneous VSNs to ensure that the models are able to track thebird at these highest altitudes.

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    Lic Thesis 86
  • 29.
    Ahmad, Naeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Khursheed, Khursheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Model, placement optimization and verification of a sky surveillance visual sensor network2013In: International Journal of Space-Based and Situated Computing (IJSSC), ISSN 2044-4893, E-ISSN 2044-4907, Vol. 3, no 3, p. 125-135Article in journal (Refereed)
    Abstract [en]

    A visual sensor network (VSN) is a distributed system of a large number of camera nodes, which generates two dimensional data. This paper presents a model of a VSN to track large birds, such as golden eagle, in the sky. The model optimises the placement of camera nodes in VSN. A camera node is modelled as a function of lens focal length and camera sensor. The VSN provides full coverage between two altitude limits. The model can be used to minimise the number of sensor nodes for any given camera sensor, by exploring the focal lengths that fulfils both the full coverage and minimum object size requirement. For the case of large bird surveillance, 100% coverage is achieved for relevant altitudes using 20 camera nodes per km² for the investigated camera sensors. A real VSN is designed and measurements of VSN parameters are performed. The results obtained verify the VSN model.

  • 30.
    Ahmad, Naeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Khursheed, Khursheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Cost Optimization of a Sky Surveillance Visual Sensor Network2012In: Proceedings of SPIE - The International Society for Optical Engineering, Belgium: SPIE - International Society for Optical Engineering, 2012, p. Art. no. 84370U-Conference paper (Refereed)
    Abstract [en]

    A Visual Sensor Network (VSN) is a network of spatially distributed cameras. The primary difference between VSN and other type of sensor network is the nature and volume of information. A VSN generally consists of cameras, communication, storage and central computer, where image data from multiple cameras is processed and fused. In this paper, we use optimization techniques to reduce the cost as derived by a model of a VSN to track large birds, such as Golden Eagle, in the sky. The core idea is to divide a given monitoring range of altitudes into a number of sub-ranges of altitudes. The sub-ranges of altitudes are monitored by individual VSNs, VSN1 monitors lower range, VSN2 monitors next higher and so on, such that a minimum cost is used to monitor a given area. The VSNs may use similar or different types of cameras but different optical components, thus, forming a heterogeneous network.  We have calculated the cost required to cover a given area by considering an altitudes range as single element and also by dividing it into sub-ranges. To cover a given area with given altitudes range, with a single VSN requires 694 camera nodes in comparison to dividing this range into sub-ranges of altitudes, which requires only 96 nodes, which is 86% reduction in the cost.

  • 31.
    Ahmad, Naeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Khursheed, Khursheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Modeling and Verification of a Heterogeneous Sky Surveillance Visual Sensor Network2013In: International Journal of Distributed Sensor Networks, ISSN 1550-1329, E-ISSN 1550-1477, p. Art. id. 490489-Article in journal (Refereed)
    Abstract [en]

    A visual sensor network (VSN) is a distributed system of a large number of camera nodes and has useful applications in many areas. The primary difference between a VSN and an ordinary scalar sensor network is the nature and volume of the information. In contrast to scalar sensor networks, a VSN generates two-dimensional data in the form of images. In this paper, we design a heterogeneous VSN to reduce the implementation cost required for the surveillance of a given area between two altitude limits. The VSN is designed by combining three sub-VSNs, which results in a heterogeneous VSN. Measurements are performed to verify full coverage and minimum achieved object image resolution at the lower and higher altitudes, respectively, for each sub-VSN. Verification of the sub-VSNs also verifies the full coverage of the heterogeneous VSN, between the given altitudes limits. Results show that the heterogeneous VSN is very effective to decrease the implementation cost required for the coverage of a given area. More than 70% decrease in cost is achieved by using a heterogeneous VSN to cover a given area, in comparison to homogeneous VSN. © 2013 Naeem Ahmad et al.

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  • 32.
    Ahmad, Naeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Khursheed, Khursheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Model and placement optimization of a sky surveillance visual sensor network2011In: Proceedings - 2011 International Conference on Broadband and Wireless Computing, Communication and Applications, BWCCA 2011, IEEE Computer Society, 2011, p. 357-362Conference paper (Refereed)
    Abstract [en]

    Visual Sensor Networks (VSNs) are networks which generate two dimensional data. The major difference between VSN and ordinary sensor network is the large amount of data. In VSN, a large number of camera nodes form a distributed system which can be deployed in many potential applications. In this paper we present a model of the physical parameters of a visual sensor network to track large birds, such as Golden Eagle, in the sky. The developed model is used to optimize the placement of the camera nodes in the VSN. A camera node is modeled as a function of its field of view, which is derived by the combination of the lens focal length and camera sensor. From the field of view and resolution of the sensor, a model for full coverage between two altitude limits has been developed. We show that the model can be used to minimize the number of sensor nodes for any given camera sensor, by exploring the focal lengths that both give full coverage and meet the minimum object size requirement. For the case of large bird surveillance we achieve 100% coverage for relevant altitudes using 20 camera nodes per km2 for the investigated camera sensors.

  • 33.
    Ahmetovic, Edvin
    University West, Department of Engineering Science.
    Estimation of Stator Temperature in an Electric Machinebased on Stator Resistance Computation2023Independent thesis Advanced level (degree of Master (One Year)), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    Due to toughened CO2 emission standards the automotive industry is approaching a transition to zero-emission mobility. An accurate estimation of the stator temperature is an essential part of the motor controls and to protect the electric motor from overheating. An inaccurate estimation leads to bigger margins between estimated value and actual value to protect the electric motor which affects the performance. A literature study was performed which presented different methods that has been used in previous work to estimate parameters of an electric machine. The purpose of this master thesis is to find a suitable method and develop a temperature observer to estimate the stator winding temperature based on a resistance observer.In the development work three different methods were tested on a single-phase electric machine for the sake of simplicity. First method assuming steady state condition, second was the Forward Euler and third zero-order hold. The results showed that the zero-order hold method using a recursive least-square (RLS) optimization was performing the best in the higher frequencies but in the lower range the steady state RLS method was better which was also the method that was used on a three-phase electric motor model from a Nissan Leaf.The sensitivity analysis showed that the estimate of the stator resistance is sensitive to errors on the input variables and that the errors are highest in the mid-torque range and in the lower part of the speed range. The error on the input variables was arbitrarily chosen of +3 % and was added separately on the inductances and voltages of the d- and q-axis 𝐿𝑑, 𝐿𝑞, 𝑣𝑑, 𝑣𝑞, the rotor speed 𝜔 and the flux-linkage 𝜑. The variable that was affecting the resistance estimation the most was when a fault of 3% was introduced on the rotor speed 𝜔 which gave an error of more than -1200% on the estimated resistance. In nominal conditions, i.e. room temperature and constant stator temperature, the results showed an accurate resistance estimation of -0.4 – 1.4 % followed by an accurate temperature estimation

  • 34.
    Ahokas, Jakob
    Linköping University, Department of Electrical Engineering.
    Automated animal behavior analysis using accelerometer activity tags2024Independent thesis Advanced level (degree of Master (Two Years)), 28 HE creditsStudent thesis
    Abstract [en]

    The agricultural sector relies heavily on livestock, and efficient management of the animals is crucial not only for economic reasons but also for ensuring animal welfare and promoting sustainable farming practices. Traditional livestock management methods such as manual supervision and remote cameras are labor-intensive and costly, particularly with large or free-roaming herds. 

    This thesis explores the integration of collar-based accelerometer activity tags with the use of machine learning models to automate the monitoring and analysis of livestock behavior, specifically focusing on cows and goats. The primary goal is to develop a system that can accurately classify various animal behaviors using data collected from 3-dimensional accelerometer sensors. 

    The methodology involves collecting accelerometer data from tagged animals, which are processed and transformed into various representations for feature extraction. A decision tree classifier, simplified from an original random forest model, is trained on this feature set to recognize different behaviors. 

    The model implementation on the system-on-chip demonstrates the feasibility of deploying these machine models on resource-constrained embedded systems. The classifier developed in this study performs well across most basic behaviors, demonstrating high accuracy in detecting activities such as eating, lying, and standing. However, some underrepresented classes in the dataset showed lower classification performance. To address this, the study uses data augmentation techniques to balance the impact of underrepresented classes and improve the model’s generalization across less frequent behaviors. The results show promise as a way to modernize agriculture by offering an automated solution for livestock monitoring, with significant implications for animal health, farm efficiency, and overall welfare. 

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  • 35.
    Aissani, D.
    et al.
    University of Bejaia, Algeria.
    Flammini, Francesco
    University of Maryland University College (UMUC) Europe, Germany.
    Editorial2017In: International Journal of Critical Computer-Based Systems, ISSN 1757-8779, E-ISSN 1757-8787, Vol. 7, no 1, p. 1-3Article in journal (Refereed)
  • 36.
    Aissani, D.
    et al.
    University of Bejaia, Algeria.
    Flammini, Francesco
    University of Maryland University College (UMUC) Europe, Germany.
    Editorial2017In: International Journal of Critical Computer-Based Systems, ISSN 1757-8779, E-ISSN 1757-8787, Vol. 7, no 1, p. 1-3Article in journal (Other academic)
  • 37.
    Aittamaa, Simon
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Programming embedded real-time systems: implementation techniques for concurrent reactive objects2011Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    An embedded system is a computer system that is a part of a larger device with hardware and mechanical parts. Such a system often has limited resources (such as processing power, memory, and power) and it typically has to meet hard real-time requirements. Today, as the area of application of embedded systems is constantly increasing, resulting in higher demands on system performance and a growing complexity of embedded software, there is a clear trend towards multi-core and multi-processor systems. Such systems are inherently concurrent, but programming concurrent systems using the traditional abstractions (i.e., explicit threads of execution) has been shown to be both difficult and error-prone. The natural solution is to raise the abstraction level and make concurrency implicit, in order to aid the programmer in the task of writing correct code. However, when we raise the abstraction level, there is always an inherent cost. In this thesis we consider one possible concurrency model, the concurrent reactive object approach that offers implicit concurrency at the object level. This model has been implemented in the programming language Timber, which primarily targets development of real-time systems. It is also implemented in TinyTimber, a subset of the C language closely matching Timber’s execution model. We quantify various costs of a TinyTimber implementation of the model (such as context switching and message passing overheads) on a number of hardware platforms and compare them to the costs of the more common thread-based approach. We then demonstrate how some of these costs can be mitigated using stack resource policy. On a separate track, we present a feasibility test for garbage collection in a reactive real-time system with automatic memory management, which is a necessary component for verification of correctness of a real-time system implemented in Timber

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  • 38.
    Aittamaa, Simon
    et al.
    Luleå University of Technology, Department of Computer Science, Electrical and Space Engineering, Embedded Internet Systems Lab.
    Eriksson, Johan
    Lindgren, Per
    Uniform scheduling of internal and external events under SRP-EDF2010In: Annual International Conference on Real-Time and Embedded Systems ( RTES 2010): 1-2 November 2010, Mandarin Orchard Hotel, Singapore, 2010Conference paper (Refereed)
    Abstract [en]

    With the growing complexity of modern embedded real-time systems, scheduling and managing of resources has become a daunting task. While scheduling and resource management for internal events can be simplified by adopting a commonplace real-time operating system (RTOS), scheduling and resource management for external events are left in the hands of the programmer, not to mention managing resources across the boundaries of external and internal events. In this paper we propose a unified system view incorporating earliest deadline first (EDF) for scheduling and stack resource policy (SRP) for resource management. From an embedded real-time system view, EDF+SRP is attractive not only because stack usage can be minimized, but also because the cost of a pre-emption becomes almost as cheap as a regular function call, and the number of preemptions is kept to a minimum. SRP+EDF also lifts the burden of manual resource management from the programmer and incorporates it into the scheduler. Furthermore, we show the efficiency of the SRP+EDF scheme, the intuitiveness of the programming model (in terms of reactive programming), and the simplicity of the implementation.

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  • 39.
    Akbari, N.
    et al.
    University of Tehran, Tehran, Iran.
    Modarressi, M.
    University of Tehran, Tehran, Iran.
    Daneshtalab, Masoud
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Sweden.
    Loni, Mohammad
    Mälardalen University, School of Innovation, Design and Engineering, Embedded Systems. Royal Institute of Technology (KTH), Sweden.
    A Customized Processing-in-Memory Architecture for Biological Sequence Alignment2018In: Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, Institute of Electrical and Electronics Engineers Inc. , 2018, article id 8445124Conference paper (Refereed)
    Abstract [en]

    Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. The design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation. 

  • 40.
    Akinola, Paul
    Linnaeus University, Faculty of Technology, Department of computer science and media technology (CM).
    Design and Implementation of an IoT Solution for Vehicle Access Control in Residential Environment2019Independent thesis Advanced level (degree of Master (One Year)), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    To overcome the hurdles associated with space management and security controls in a housing system, research was projected to study and analyze the necessary factors of accomplishment. Over time, different processes were observed and reviewed to make this a possible deal. Various residents were interviewed on the daily constraints in parking and managing their vehicles within their housing premises. The reported daunting concern was majorly the gate access and personal hunts for the space to keep the individual resident’s cars. Every resident would always have to stop and hoot at the housing gate for the assigned personnel to check and open the gate. While this would waste every resident’s time, the visitors even face more delay often time. Hitherto, car access and parking constraint become a thing of worry that no one would want to engage the housing service anymore. The interest has got dwindled. And to re-awaken the high patronage of the housing system, a gap must be bridged with an immediate solution to space management with a gating system. These were subsequently given a classical thought, while a prototype solution was demonstrated and reviewed with the various residents of some selected housing. This received a high welcoming embracement and was beckoned to be made real by the logical heuristic. At this point, nothing was further considered than using the Internet of things (IoT) technology to implement Vehicular Access Management for the control and integration of intended space provisioning in any housings. Consequently, the number plate of every vehicle becomes the automatic access tag and would be used for security control within the housing location. Vehicles’ numbers would be captured and used to manage the residents passing through the automated gating system. With it, records would be made for all permitted residents and the visitors that own a car. Thus, a proper arrangement would be allotted accordingly, as provisioned by the gating system administrator.

    However, to allegories the above-proffered solution, this project work is divided into six sections. The introductory section introduces the project rationale, lists the objectives, explores related works, and introduces how IoT and vehicular systems can be merged. The second section delves into these vehicular systems. It introduces the Automatic License Plate Recognition System (ALRP) and the Raspberry Pi and highlights the merits of the Integrated Vehicular Access Security System. Open-CV and machine learning are also introduced. Section three covers the solution design, while section four is the implementation phase. Section five covers the testing and implementation of the solution. The final section summarizes the project. The project successfully models an automated solution for the security of tenants and vehicle users against unauthorized access to residential estates and buildings.

  • 41.
    Al Hayani, Musab
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Modeling Bus Load on CAN2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The existence of high load and latency in the CAN bus network would indeed lead to a situation where a given message crosses its deadline; this situation would disturb the continuity of the required service as well as activating fault codes due to delay of message delivery, which might lead to system failure.

    The outcome and goal of this thesis is to research and formulate methods to determine and model busload and latencies, by determining parameters such as alpha and breakdown utilization, which are considered as indications to the start of network breakdown when a given message in a dataset start to introduce latency by crossing its deadline which are totally prohibited in critical real time communications.

    The final goal of this master thesis is to develop a TOOL for calculating, modeling, determining and visualizing worst case busload, throughput, networks’ breakdown points and worst case latency in Scania CAN bus networks which is based on the J1939 protocol.

    SCANLA (The developed CAN busload analyzer tool in this thesis) is running as an executable application and uses a Graphical User Interface as a human-computer interface (i.e., a way for humans to interact with the tool) that useswindows,icons and menus and which can be manipulated by a mouse.

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  • 42.
    Al Mamun, Abdullah
    et al.
    Division of Software Engineering Chalmers University of Technology and University of Gothenburg, Gothenburg, Sweden.
    Berger, Christian
    Division of Software Engineering Chalmers University of Technology and University of Gothenburg, Gothenburg, Sweden.
    Hansson, Jörgen
    University of Skövde, School of Informatics. University of Skövde, The Informatics Research Centre.
    Explicating, Understanding and Managing Technical Debt from Self-Driving Miniature Car Projects2014In: Proceedings 2014 6th IEEE International Workshop on Managing Technical Debt: MTD 2014, Los Alamitos, CA: IEEE Computer Society, 2014, p. 11-18Conference paper (Refereed)
    Abstract [en]

    Technical debt refers to various weaknesses in the design or implementation of a system resulting from trade-offs during software development usually for a quick release. Accumulating such debt over time without reducing it can seriously hamper the reusability and maintainability of the software. The aim of this study is to understand the state of the technical debt in the development of self-driving miniature cars so that proper actions can be planned to reduce the debt to have more reusable and maintainable software. A case study on a selected feature from two self-driving miniature car development projects is performed to assess the technical debt. Additionally, an interview study is conducted involving the developers to relate the findings of the case study with the possible root causes. The result of the study indicates that "the lack of knowledge" is not the primary reason for the accumulation of technical debt from the selected code smells. The root causes are rather in factors like time pressure followed by issues related to software/hardware integration and incomplete refactoring as well as reuse of legacy, third party, or open source code.

  • 43.
    Alam, Ashraful
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Parallelization of the Estimation Algorithm of the 3D Structure Tensor2012Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    This thesis work provides the implementation of 3D structure tensor on a Massively Parallel Processor Array (MPPA), Ambric 2045.

     

    The 3D structure tensor algorithm is often used in image processing applications to compute the optical flow or to detect local 3D structures and their directions. The 3D structure tensor algorithm (3D-STA) consists of three main parts: gradient, tensor and smoothing. This algorithm is computationally expensive due to many multiplications and additions which are required to calculate the gradient (edge), the tensor and to smooth every pixel of the image. This is why this algorithm is very slow to run on a single processor. Therefore, it is important to make it parallel for high performance computation.

     

    This thesis provides two parallel implementations of 3D-STA; namely coarse-grained parallelism and fine-grained parallelism. Ambric has 336 processors. Only 49 processors are used in coarse-grained implementation and 165 processors are used in fine-grained implementation. The performance of the two implementations is measured using a video stream input, consisting of a sequence of images of size 20x256x256. The performance of the coarse-grained parallelism implementation is 25 frames per second (fps) and the one of the fine-grained parallelism implementation is 100 fps. Thus the fine-grained version is four time faster than the coarse-grained one.

     

    Additionally, the results are compared with the result of the Matlab implementation, running on Intel(R) Core 2 duo @2.10 GHz processor and also compared with another parallel optical flow implementation, in terms of speed and efficiency. The coarse-grained implementation is 58 times faster than the Matlab implementation and it achieves approximately half of the performance of the other parallel optical flow implementation. On the other hand, the fine-grained implementation is 230 times faster than the Matlab implementation and more than twice as (100/43) fast as the other parallel optical flow implementation.

     

    These performance results are satisfactory and the results that our parallel implementations can be considered for real-time applications.

     

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  • 44.
    Alam, Ashraful
    et al.
    Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE).
    Ul-Abdin, Zain
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Svensson, Bertil
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS), Centre for Research on Embedded Systems (CERES).
    Parallelization of the Estimation Algorithm of the 3D Structure Tensor2012In: 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012 / [ed] Peter Athanas, René Cumplido & Eduardo de la Torre, Piscataway, N.J.: IEEE Press, 2012, article id 6416771Conference paper (Refereed)
    Abstract [en]

    The three dimensional structure tensor algorithm (3D-STA) is often used in image processing applications to compute the optical flow or to detect local 3D structures and their directions. This algorithm is computationally expensive due to many computations that are required to calculate the gradient, the tensor, and to smooth every pixel of the image frames. Therefore, it is important to parallelize the implementation to achieve high performance. In this paper we present two parallel implementations of 3D-STA; namely moderately parallelized and highly parallelized implementation, on a massively parallel reconfigurable array. Finally, we evaluate the performance of the generated code and results are compared with another optical flow implementation. The throughput achieved by the moderately parallelized implementation is approximately half of the throughput of the Optical flow implementation, whereas the highly parallelized implementation results in a 2x gain in throughput as compared to the optical flow implementation. © 2012 IEEE.

  • 45.
    Alam, Assad
    et al.
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Asplund, Fredrik
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Behere, Sagar
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Björk, Mattias
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Garcia Alonso, Liliana
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Khaksari, Farzad
    KTH, School of Electrical Engineering (EES), Signal Processing.
    Khan, Altamash
    KTH, School of Electrical Engineering (EES), Signal Processing.
    Kjellberg, Joakim
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Liang, Kuo-Yun
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Lyberger, Rickard
    Scania CV AB.
    Mårtensson, Jonas
    KTH, School of Electrical Engineering (EES), Automatic Control. KTH, School of Electrical Engineering (EES), Centres, ACCESS Linnaeus Centre.
    Nilsson, John-Olof
    KTH, School of Electrical Engineering (EES), Signal Processing.
    Pettersson, Henrik
    Scania CV AB.
    Pettersson, Simon
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Stålklinga, Elin
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Sundman, Dennis
    KTH, School of Electrical Engineering (EES), Signal Processing.
    Zachariah, Dave
    KTH, School of Electrical Engineering (EES), Signal Processing.
    Cooperative driving according to Scoop2011Report (Other academic)
    Abstract [en]

    KTH Royal Institute of Technology and Scania are entering the GCDC 2011 under the name Scoop –Stockholm Cooperative Driving. This paper is an introduction to their team and to the technical approach theyare using in their prototype system for GCDC 2011.

  • 46.
    Alam, Mohammad Anzar
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thim, Jan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Manuilskiy, Anatoliy
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Westerlind, Christina
    SCA R&D Centre, Sundsvall, Sweden.
    Lindgren, Johan
    Iggesund Paperboard AB, Iggesund, Sweden.
    Lidén, Joar
    SCA Ortviken AB, Sundsvall, Sweden.
    Investigation of the surface topographical differences between the Cross Direction and the Machine Direction for newspaper and paperboard2011In: Nordic Pulp & Paper Research Journal, ISSN 0283-2631, E-ISSN 2000-0669, Vol. 26, no 4, p. 468-475Article in journal (Refereed)
    Abstract [en]

    Paper and paperboard surface quality is constantly being improved by the industry. This improvement work deals with the essential fact that the surface topography must be measured, both in relation to offline and online measurements for the manufactured products. Most measurements relating to surface topography (especially online) are performed either in the machine direction (MD) or in the cross direction (CD). It has been the opinion of SCA Ortviken AB and Iggesund Paperboard AB that the surface topography amplitudes are almost always higher in the CD than in the MD, for their products which consist of newspaper and paperboard. This article aims to investigate the rela-tionship between the CD and the MD surface topography amplitudes for a wide range of spatial wavelength for both newspaper and paperboard. The tests and investiga-tions have been conducted using an FRT Microprof profilometer within the range 20 μm up to 8 mm, and the results confirm that the surface topography amplitudes are higher in the CD for most of the shorter spatial wavelength within this range. The results also show significant differences between measurements for different paper qualities, suggesting a requirement to investigate the relationship between the CD and the MD topography for all paper and paperboard qualities of interest for a paper or paperboard mill, before a decision is made in relation to a measurement method.

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  • 47.
    Alendal, Gunnar
    et al.
    NTNU, Gjøvik, Norway.
    Dyrkolbotn, Geir Olav
    NTNU, Gjøvik, Norway & Norwegian Defence Cyber Academy (NDCA), Jørstadmoen, Norway.
    Axelsson, Stefan
    Halmstad University, School of Information Technology, Halmstad Embedded and Intelligent Systems Research (EIS).
    Forensics acquisition – Analysis and circumvention of samsung secure boot enforced common criteria mode2018In: Digital Investigation. The International Journal of Digital Forensics and Incident Response, ISSN 1742-2876, E-ISSN 1873-202X, Vol. 24, no Suppl., p. S60-S67Article in journal (Refereed)
    Abstract [en]

    The acquisition of data from mobile phones have been a mainstay of criminal digital forensics for a number of years now. However, this forensic acquisition is getting more and more difficult with the increasing security level and complexity of mobile phones (and other embedded devices). In addition, it is often difficult or impossible to get access to design specifications, documentation and source code. As a result, the forensic acquisition methods are also increasing in complexity, requiring an ever deeper understanding of the underlying technology and its security mechanisms. Forensic acquisition techniques are turning to more offensive solutions to bypass security mechanisms, through security vulnerabilities. Common Criteria mode is a security feature that increases the security level of Samsung devices, and thus make forensic acquisition more difficult for law enforcement. With no access to design documents or source code, we have reverse engineered how the Common Criteria mode is actually implemented and protected by Samsung's secure bootloader. We present how this security mode is enforced, security vulnerabilities therein, and how the discovered security vulnerabilities can be used to circumvent Common Criteria mode for further forensic acquisition. © 2018 The Author(s). Published by Elsevier Ltd on behalf of DFRWS.

  • 48.
    Alexander, Karlsson
    Mälardalen University, School of Innovation, Design and Engineering.
    Design and Development of a Wireless Multipoint E-stop System for Autonomous Haulers2018Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    Safety-related functions are important in autonomous industrial applications and are featured in an extensive body of work contained within the standards. The implementation of safety-related systems is commonly done by an external company at a great cost and with limited flexibility. Thus, the objective of this thesis was to develop and implement a safety-related system using o-the-shelf products and to analyse how well it can comply with the established standards of safety-related functions. This work has sought to review the current standards for safety-functions, the eectsof harsh radio environments on safety-related systems, and how to validate the safety-function.The system development process was used to gain knowledge by rst building the concept based on pre-study. After the pre-study was nished, the process moved to the development of software, designed to maintain a wireless heartbeat as well as to prevent collisions between the autonomous and manual-driven vehicles at a quarry, and implementation of the system in real hardware. Finally, a set of software (simulations) and hardware (measurements in an open-pit mine) tests were performed to test the functionality of the system. The wireless tests showed that the system adhered to the functional requirements set by the company, however, the evaluated performance level according to ISO 13849-1 resulted in performance level B which is insucient for a safety-related function. This work demonstrates that it is not possible to develop a safety-related system using the off-the-shelf products chosen, without hardware redundancy.

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  • 49.
    Alexandersson, Johan
    et al.
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Nordin, Olle
    Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, Faculty of Science & Engineering.
    Implementation of CAN Communication Stack in AUTOSAR2015Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    In the automotive industry today, embedded systems have reached a level of complexity which is not maintainable with the traditional approach of design- ing automotive embedded systems. For this purpose, many of the worlds leading automotive manufacturers have formed an alliance to apprehend this problem. This has resulted in AUTOSAR, an open standardized architecture for automotive embedded systems, which strives for increased flexibility and safety regulations. This thesis will explore the possibilities of implementing a CAN Communication stack using the AUTOSAR architecture and its corresponding methodology. As a result of this thesis, a complete AUTOSAR CAN communication stack has been implemented, as well has a simulator application with the purpose of testing its functionality. 

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  • 50.
    Alexandersson, Josua
    et al.
    Jönköping University, School of Engineering, JTH, Department of Computer Science and Informatics.
    Persson, Jesper
    Jönköping University, School of Engineering, JTH, Department of Computer Science and Informatics.
    Utforskning utav Linux roll i att Accelerera Tid till Marknaden för Inbyggda System2023Independent thesis Basic level (degree of Bachelor), 10 credits / 15 HE creditsStudent thesis
    Abstract [en]

    How can Linux reduce the time required for development in embedded systems, and what makes Linux appealing to embedded developers despite the loss in overall control? Through qualitative interviews with industry professionals and a systematic literature review, challenges and benefits of using Linux in embedded systems development were identified and discussed. Three hypotheses were formulated based on recurring topic agreement among the interview subjects: Reduced development time through the use of open-source solutions, struggles with real-time and security requirements, and challenges within troubleshooting and dependency management. The empirical data observed primarily aligned with the professional perception indicating the potential for development time reduction leveraging resources properly. However also highlighting additional challenges that are not present in traditional embedded system development. Several trade-offs were observed from the findings, including increased overhead and licensing concerns. Further research is required to fully understand the advantages, challenges and limits associated with Linux in an embedded system environment. This study provides valuable insights for future exploration within the field. 

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