Organizations relying on Information Technology for their business processes have to employ various Security Mechanisms (Authentication, Authorization, Hashing, Encryption etc) to achieve their organizational security objectives of data confidentiality, integrity and availability. These security mechanisms except from their intended role of increased security level for this organization may also affect other systems outside the organization in a positive or negative manner called externalities. Externalities emerge in several ways i.e. direct cost, direct benefit, indirect cost and indirect benefit. Organizations barely consider positive externalities although they can be beneficial and the negative externalities that could create vulnerabilities are simply ignored. In this paper, we will present an infrastructure to streamline information security externalities that appear dynamically for an organization

Nowadays hardware components are very expensive, especially if the prime purpose is to perform some routing related lab exercises. Physically connected network resources are required to get the desired results. Configuration of network resources in a lab exercise consumes much time of the students and scientists. The router simulation package Crab(1), based on KnoppW, Quagga' and User Mode Linux (UML) is designed for the students to facilitate them in performing lab exercises on a standalone computer where no real network equipment is needed. In addition to that it provides the facility of connection with the real network equipments. Crab also handles the pre configuration of different parts of the simulated networks like automatic IT addressing etc. This paper will describe the performance enhancing of Crab by replacing User Mode Linux virtual machine with XEN capable of providing ten virtual sessions concurrently using a standalone computer.

The constantly rising threats in IT infrastructure raise many concerns for an organization, altering security requirements according to dynamically changing environment, need of midcourse decision management and deliberate evaluation of security measures are most striking. Common Criteria for IT security evaluation has long been considered to be victimized by uncertain IT infrastructure and considered resource hungry, complex and time consuming process. Considering this aspect we have continued our research quest for analyzing the opportunities to empower IT security evaluation process using Real Options thinking. The focus of our research is not only the applicability of real options analysis in IT security evaluation but also observing its implications in various domains including IT security investments and risk management. We find it motivating and worth doing to use an established method from corporate finance i.e. real options and utilize its rule of thumb technique as a road map to counter uncertainty issues for evaluation of IT products. We believe employing options theory in security evaluation will provide the intended benefits. i.e. i) manage dynamically changing security requirements ii) accelerating evaluation process iii) midcourse decision management. Having all the capabilities of effective uncertainty management, options theory follows work procedures based on mathematical calculations quite different from information security work processes. In this paper, we will address the diversities between the work processes of security evaluation and real options analysis. We present an adaptability infrastructure to bridge the gap and make them coherent with each other. This liaison will transform real options concepts into a compatible mode that provides grounds to target IT security evaluation and common criteria issues. We will address ESAM system as an example for illustrations and applicability of the concepts.

Reliability of IT systems and infrastructure is a critical need for organizations to trust their business processes. This makes security evaluation of IT systems a prime concern for these organizations. Common Criteria is an elaborate, globally accepted security evaluation process that fulfills this need. However CC rigidly follows the initial specification and security threats and takes too long to evaluate and as such is also very expensive. Rapid development in technology and with it the new security threats further aggravates the long evaluation time problem of CC to the extent that by the time a CC evaluation is done, it may no longer be valid because new security threats have emerged that have not been factored in. To address these problems, we propose a novel Option Based Evaluation methodology for security of IT systems that can also be considered as an enhancement to the CC process. The objective is to address uncertainty issues in IT environment and speed up the slow CC based evaluation processes. OBE will follow incremental evaluation model and address the following main concerns based on options theory i.e. i) managing dynamic security requirement with mid-course decision management ii) devising evaluation as an improvement process iii) reducing cost and time for evaluation of an IT product.

Information security has long been considered as a key concern for organizations benefiting from the electronic era. Rapid technological developments have been observed in the last decade which has given rise to novel security threats, making IT, an uncertain infrastructure. For this reason, the business organizations have an acute need to evaluate the security aspects of their IT infrastructure. Since many years, CC (Common Criteria) has been widely used and accepted for evaluating the security of IT products. It does not impose predefined security rules that a product should exhibit but a language for security evaluation. CC has certain advantages over ITSEC1, CTCPEC2 and TCSEC3 due to its ability to address all the three dimensions: a) it provides opportunity for users to specify their security requirements, b) an implementation guide for the developers and c) provides comprehensive criteria to evaluate the security requirements. Among the few notable shortcomings of CC is the amount of resources and a lot of time consumption. Another drawback of CC is that the security requirements in this uncertain IT environment must be defined before the project starts. ROA is a well known modern methodology used to make investment decisions for the projects under uncertainty. It is based on options theory that provides not only strategic flexibility but also helps to consider hidden options during uncertainty. ROA comes in two flavors: first for the financial option pricing and second for the more uncertain real world problems where the end results are not deterministic. Information security is one of the core areas under consideration where researchers are employing ROA to take security investment decisions. In this paper, we give a brief introduction of ROA and its use in various domains. We will evaluate the use of Real options based methods to enhance the Common Criteria evaluation methodology to manage the dynamic security requirement specification and reducing required time and resources. We will analyze the possibilities to overcome CC limitations from the perspective of the end user, developer and evaluator. We believe that with the ROA enhanced capabilities will potentially be able to stop and possibly reverse this trend and strengthen the CC usage with a more effective and responsive evaluation methodology.

The recent development for multimedia applications on mobile terminals raised the need for flexible and scalable computing platforms that are capable of providing considerable (application specific) computational performance within a low cost and a low energy budget. The MPSoC with multi-disciplinary approach, resolving application mapping, platform architecture and runtime management issues, provides such multiple heterogeneous, flexible processing elements. In MPSoC, the run-time manager takes the design time exploration information as an input and selects an active Pareto point based on quality requirement and available platform resources, where a Pareto point corresponds to a particular parallelization possibility of target application. To use system’s scalability at best and enhance application’s flexibility a step further, the resource management and Pareto point selection decisions need to be adjustable at run-time. This thesis work experiments run-time Pareto point switching for MPEG-4 encoder. The work involves design time exploration and then embedding of two parallelization possibilities of MPEG-4 encoder into one single component and enabling run-time switching between parallelizations, to give run-time control over adjusting performance-cost criteria and allocation de-allocation of hardware resources at run-time. The newer system has the capability to encode each video frame with different parallelization. The obtained results offer a number of operating points on Pareto curve in between the previous ones at sequence encoding level. The run-time manager can improve application performance up to 50% or can save memory bandwidth up to 15%, according to quality request.

The success of the P2P idea has created a huge diversity of approaches, among which overlay networks, for example, Gnutella, Kazaa, Chord, Pastry, Tapestry, P-Grid, or DKS, have received specific attention from both developers and researchers. A wide variety of algorithms, data structures, and architectures have been proposed. The terminologies and abstractions used, however have become quite inconsistent since the P2P paradigm has attracted people from many different communities, e.g., networking, databases, distributed systems, graph theory, complexity theory, biology, etc. In this paper we propose a reference model for overlay networks which is capable of modeling different approaches in this domain in a generic manner It is intended to allow researchers and users to assess the properties of concrete systems, to establish a common vocabulary for scientific discussion, to facilitate the qualitative comparison of the systems, and to serve as the basis for defining a standardized API to make overlay networks interoperable.

In this paper we propose and evaluate algorithms for placement of routers in a wireless sensor network. There are two major requirements on router placement First, a placement must guarantee connectivity, i.e. every sensor must be able to communicate through routers with a predefined computer-connected gateway node. Second, a placement must provide robust communication in the case of router failures. This is achieved by placing redundant routers that increase the number of possible routes. Both requirements should be met by placing as few routers as possible. The proposed algorithms compute placement in an efficient and reasonably fast way.

On-chip power distribution network model for simultaneous switching of 3D ICs stacked through TSVs to choose TSV pattern, maximum number of chips in a stack and location of the decoupling capacitor for early design trade-offs.

The last two decades have witnessed the birth of revolutionary technologies in data communications including wireless technologies, System on Chip (SoC), Multi Processor SoC (MPSoC), Network on Chip (NoC), and more. At the same time we have witnessed that performance does not always keep pace with expectations in many services like multimediaservices and biomedical applications. Moreover, the IT market has suffered from some crashes. Hence, this triggered us to think of making use of available technologies and developing new ones so that the performance level is suitable for given applications and services. In the medical field, from a statistical viewpoint, the biggest diseases in number of deaths are heart diseases, namely Cardiovascular Disease (CVD) and Stroke. The application with the largest market for CVD is the electrocardiogram (ECG/EKG) analysis. According to the World Health Organization (WHO) report in 2003, 29.2% of global deaths are due to CVD and Stroke, half of which could be prevented if there was proper monitoring. We found in the new advance in microelectronics, NoC, SoC, and MPSoC, a chance of a solution for such a big problem. We look at the communication technologies, wireless networks, and MPSoC and realize that many projects can be founded, and they may affect people's lives positively, as for example, curing people more rapidly, as well as homecare of such large scale diseases. These projects have a medical impact as well as economic and social impacts. The intention is to use performance analysis of interconnected microelectronic systems and combine it with MPSoC and NoC technologies in order to evolve to new systems on chip that may make a difference. Technically, we aim at rendering more computations in less time, on a chip with smaller volume, and with less expense. The performance demand and the vision of having a market success, i.e. contributing to lower healthcare costs, pose many challenges on the hardware/software co-design to meet these goals. This calls upon the development of new integrated circuits featuring increased energy efficiency while providing higher computation capabilities, i.e. better performance. The biomedical application of ECG analysis is an ideal target for an application-specific SoC implementation. However, new 12-lead ECG analyses algorithms are needed to meet the aforementioned goals. In this thesis, we present two novel algorithms for ECG analysis, namely the Autocorrelation-Function (ACF) based algorithm and the Fast Fourier Transform (FFT) based algorithm. In this respect, we explore the design space by analyzing different hardware and software architectures. As a result, we realize a design with twelve processors that can compute 3.5 million arithmetic computations and respect the real time hard deadline for our biomedical application (3.5-4seconds), and that can deploy the ACF-based and FFT-based algorithms. Then, we investigate the configuration space looking for the most effective solution, performance and energy-wise. Consequently, we present three interconnect architectures (Single Bus, Full Crossbar, and Partial Crossbar) and compare them with existing solutions. The sampling frequencies of 2.2 KHz and 4 KHz, with 12 DSPs, are found to be the critical points for our Shared-Bus design and Crossbar architecture, respectively. We also show how our performance analysis methods can be applied to such a field of SoC design and with a specific purpose application in order to converge to a solution that is acceptable from a performance viewpoint, meets the real-time demands, and can be implemented with the present technologies while at the same time paving the way for easier and faster development. In order to connect our MPSoC solution to communication networks to transmit the medical results to a healthcare center, we come up with new protocols that will allow the integration of multiple networks on chips in a communication network. Finally, we present a methodology for HW/SW Codesign for application-specific systems (with focus on biomedical applications) that require a large number of computations since this will foster the convergence to solutions that are acceptable from a performance point of view.

The interest in high performance chip architectures for biomedical applications is gaining a lot of research and market interest. Heart diseases remain by far the main cause of death and a challenging problem for biomedical engineers to monitor and analyze. Electrocardiography (ECG) is an essential practice in heart medicine. However, ECG analysis still faces computational challenges, especially when 12 lead signals are to be analyzed in parallel, in real time, and under increasing sampling frequencies. Another challenge is the analysis of huge amounts of data that may grow to days of recordings. Nowadays, doctors use eyeball monitoring of the 12-lead ECG paper readout, which may seriously impair analysis accuracy. Our solution leverages the advance in multi-processor system-on-chip architectures, and it is centered on the parallelization of the ECG computation kernel. Our Hardware- Software (HW/SW) Multi-Processor System-on-Chip (MPSoQ design improves upon state-of-the-art mostly for its capability to perform real-time analysis of input data, leveraging the computation horsepower provided by many concurrent DSPs, more accurate diagnosis of cardiac diseases, and prompter reaction to abnormal heart alterations. The design methodology to go from the 12-lead ECG application specification to the final HW/SW architecture is the focus of this paper. We explore the design space by considering a number of hardware and software architectural variants, and deploy industrial components to build up the system.

High-end biomedical applications are a good target for specific-purpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring andanalysis is an immediate example with a large potential market. Today, the lack of scalable hardware platforms limits real-time analysis capabilities of most portable ECG analyzers, and prevents the upgrade of analysis algorithms for better accuracy. Multiprocessor system-on-chip (MPSoC) technology, which is becoming main-stream in the domain of high-performance microprocessors, is becoming attractive even for power-constrained portable applications, due to the capability to provide scalable computation horsepower at an affordable power cost. This paper illustrates one of the first comprehensive HW/SW exploration frameworks to fully exploit MPSoC technology to improve the quality of real-time ECG analysis.

In this paper we discuss various control loop patterns for managing distributed applications with multiple control loops. We introduce a high-level framework, called DCMS, for developing, deploying and managing component-based distributed applications in dynamic environments. The control loops, and interactions among them, are illustrated in the context of a distributed self-managing storage service implemented using DCMS to achieve various self-* properties. Different control loops are used for different self-* behaviours, which illustrates one way to divide application management, which makes for both ease of development and for better scalability and robustness when managers are distributed. As the multiple control loops are not completely independent, we demonstrate different patterns to deal with the interaction and potential conflict between multiple managers.

Deploying and managing distributed applications in dynamic Grid environments requires a high degree of autonomous management. Programming autonomous management in turn requires programming environment support and higher level abstractions to become feasible. We present a framework for programming self-managing component-based distributed applications. The framework enables the separation of application’s functional and non-functional (self-*) parts. The framework extends the Fractal component model by the component group abstraction and one-to-any and one-to-all bindings between components and groups. The framework supports a network-transparent view of system architecture simplifying designing application self-* code. The framework provides a concise and expressive API for self-* code. The implementation of the framework relies on scalability and robustness of the Niche structured p2p overlay network. We have also developed a distributed file storage service to illustrate and evaluate our framework.

Paper substrate is one of the paramount nominees for Radio Frequency Identification (RFID) tags but at the same time it is extremely prone towards environmental changes. In this paper, antennas for UHF RFID tags on paper based substrate are investigated and analyzed for the first time to evaluate the effect of change in dielectric constant on the antenna parameters and performance. On the basis of analysis a concrete meander line antenna is proposed, designed and evaluated which has tremendous immunity towards variation in dielectric constant.

This paper describes a novel Flexo, Screen and Inkjet printed rounded edges bowtie antenna with T-matching stubs on paper, Kapton (HN) and Teonex Q51 substrate. Paper is one of the paramount nominees for Radio Frequency Identification (RFID) tags, for the reason that it is one of the widely and the cheapest available substrates. Kapton (HN) and Teonex Q51 are distinguished for their flexibility and reliability. The antenna exhibits compact size with outstanding read range of 4 meters and complete coverage of UHF RFID band (860-960 MHz). The results show extreme immunity of versatile antenna against harsh environments. These antennas are flexible which give autonomy for their applications.

Radio frequency identification (RFID) antenna's versatility in terms of complete coverage of UHF RFID band (860-960 MHz), while keeping the cost factor low, is an important aspect of today's growing demand for security and tracking of multiple objects in a very short time in addition to tag's readability across the globe. This paper presents a novel inkjet printed rounded corner bowtie antenna with T-matching stubs on paper substrate which is the cheapest and widest available substrate. The antenna exhibits compact size with outstanding read range.

Paper substrate is one of the paramount nominees for Radio Frequency Identification (RFID) tags, for the reason that it is one of the widely and the cheapest available substrates. In this paper, for the first time quadrate bowtie antennas with round corners [1] are realized and analyzed on paper substrate for UHF RFID tags. These inkjet printed antennas exhibit high performance which give freedom for their applications. Their area is smaller than the general triangle bowtie antenna and have advantages of smaller area, better return loss in high frequency and higher gain in normal direction of antenna plane compared with general triangular bowtie antenna.d

In this paper meander line antennas with end tip loading, designed for UHF RFID tags are presented. These novel antennas are screen printed on Kapton HN for European frequency band (866-868 MHz) and for North American frequency band (902-928 MHz). Asahi ink is used for screen printing of 25 mu m thick antenna traces which remains conductive even after several times sharp bending of these tag antennas. The results show that the antennas exhibit high performance regarding smaller area, high realized gain and better return loss in the frequency band of interest. These antennas are extremely flexible which give autonomy for their applications.

Next generation wireless communications terminals will demand the use of advanced component integration processes and high density packaging technologies in order to reduce size and to increase performance. This paper presents high density multilayer interconnects and integrated passives used to design high performance prototype filter for 5GHz wireless LAN receiver realized on MCM-D substrate. The thin film implementation of Multichip Module technology is identified as a useful platform for the integration of GaAs MMIC and silicon device technologies for microwave applications where performance, size and weight are critical factors. The ability of the MCM-D technology to provide controlled impedance, microstrip structures and integrated thin film passive components with useful performance in the microwave frequency regime has now been demonstrated.

Wireless transceivers combining several standards in one unit are of key importance. In order to reach the ultimate goal of maximizing the performance-to-cost ratio of such modules, a careful study of the target application, the architecture, and the frequency planning is strongly required. One of the most challenging tasks is the implementation of the frequency synthesizer. This challenge is compounded by the traditional technical difficulties in designing frequency synthesizers as well as the new requirements that include multi-standard support. As a result, studying the upper levels of the communication system becomes mandatory in order to frame the requirements of the frequency synthesizer and to provide a viable solution from a user’s perspective for an always-best-connected scenario. Additionally, the study of the upper layers opens up new opportunities for innovation at the lower layers, especially at the physical layer where the view is traditionally restricted by some harsh requirements whose source might not be clear at least for the physical-level designer. The first aim of this work is to provide a holistic view of how an optimum user experience can be achieved and how this affects the design of frequency synthesizers for the next generation networks. The work is heavily based on the existing garden of wireless standards although it can also serve for other applications such as real software-defined radios and dynamic spectrum allocation. As a result, this work cuts a vertical path starting from the best user experience vision down to the physical layer where it expands on the design of the frequency synthesizer. It proposes a wireless front-end solution that can make the vision of an always-best-connected scenario a reality. The architecture is based on a wireless detector called Sniffer that searches for an alternative connection while the main connection is running. Not only is the Sniffer solution viable at the physical level, but it also provides a stepping stone for development towards fully-enabled multi-standard transceivers. After this, and inline with the previous vision, some important frequency synthesizer parameters are pointed out and enhancements on the phase-locked architectures are presented. This includes ways to extend the range of the frequency synthesizer and ways to make the synthesizer adaptable depending on the requirements of the wireless standards. This work leads directly to the implementation of a multi-standard frequency synthesizer where the details of the top-down design procedure are presented at several levels of abstraction. In order to round-up the work, and due to the fact that the requirements of the frequency synthesizer stretch thin the capabilities of the technology used, calibration techniques to increase the yield of such a complicated sub-system are presented, an important step towards first-pass success.

This paper presents a direct conversion RF receiver front-end supporting the WiMAX standard. The front-end is implemented in 0.18um CMOS technology and designed using the ARCHER software. It shows how the design flow can be accelerated starting from the standard specifications and going down to schematics. All this is accompanied by test benches to extract the relevant metrics. This front-end provides a total gain of 31dB, a noise figure of 3.3dB, an IIP2 of 49.5dBm, and an IIP3 of -13.8dBm.

Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between FPGA and ASICs for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions.

The first contribution of this work is a Design Space Exploration (DSE) of the FPCAs and the identification of trade-offs between different parameters which describe them. Methods for analyzing and pruning the design space are proposed to enable a smart exploration. Finally, a set of best performing architectures in terms of area and delay is determined.

Secondly, a study of possible integration schemes to build a hybrid FPGA/FPCA chip is performed. The goal is to find a solution with optimal usage of on-chip silicon area. The advantages and disadvantages of each solution are studied and a new integration solution based on properties of FPCAs is suggested. A VLSI implementation proves the applicability of the proposed solutions.

We present an analytical method for analyzing and dimensioning a network based communication architecture. The method is based on the classic (a, p) network calculus. We use a TDMA approach for creating logically separated networks which makes statistical methods possible for calculations on Best Effort traffic, and supports implementation of Guaranteed Bandwidth services by using Virtual Circuits with Looped Containers.

Ubiquitous computing and Internet-of-Things (IoT) implies an untapped opportunity in the realm of information and communication technology, in which a large number of micro-devices with communication and/or computing capabilities, provides connectivity for anything, by anyone at anytime and anywhere. Especially, these devices can be equipped with sensors and actuators that interact with our living environment. Barcode, smart contactless card, Radio Frequency Identification (RFID) systems, wireless sensor network (WSN), and smart mobile phones are some examples which can be utilized in ubiquitous computing. RFIDs and WSN have been recognized as the two promising enablers for realization of ubiquitous computing. They have some great features such as low-cost and small- size implementation, non-line of sight operation, sensing possibilities, data storing ability, and positioning. However, there are several challenges which need to be addressed, such as limited life time for battery powered device, maintenance cost, longer operation range, higher data rate, and operation in dense multipath and multiuser environment. Ultra-Wideband Impulse Radio (UWB-IR) with its huge advantages has been recognized as a great solution for future WSN and RFID. UWB-IR technique has the possibility of achieving Gb/s data rate, hundreds of meter operation range, pJ energy per bit, centimeter accuracy of positioning, and low cost implementation. In this work utilization of UWB-IR in WSN and RFID is investigated. A wireless sensor network based on UWB-IR is proposed focusing on low-cost and low-power implementation. Our contribution is to imply two different architectures in base station and sensor nodes to satisfy power, complexity and cost constraints. For sensor nodes, an autonomous UWB-IR detection is proposed, which detects the UWB signal autonomously and no restrict synchronization is required. It reduces the circuit complexity significantly. The performance in term of bit-error-rate is compared with two other common detection techniques. It is shown that the new detection is more robustness to timing jitter and clock skew, which consequently reduces the clock and synchronization requirements considerably. A novel wireless sensing and identification system, based on remote-powered tag with asymmetric wireless link, is proposed. Our innovative contribution is to deploy two different UWB and UHF communication techniques in uplink and downlink respectively. In the proposed system, tags capture the required power supply from different environmental sources (e.g. electromagnetic wave transmitted by a reader) and transmit data through an ultra-low power impulse UWB link. A new communication protocol is devised based on slotted-aloha anti-collision algorithm. By introducing several improvements including of pipelined communication, adaptive frame size, and skipping idle slots, the system throughput of more than 2000 tags/s is achieved. To prove the system concept a single chip integrated tag is implemented in UMC 0.18μm CMOS process. The measurement results show the minimum sensitivity of -18.5 dB (14.1 μW) and adaptive data rate up to 10 Mb/s. It corresponds to 13.9 meters operation range, considering 4W EIRP, a matched antenna to the tag with 0dB gain, and free space path loss. This is a great improvement in operation range and data rate, compared with conventional passive RFID, which data rate is limited to a few hundreds of Kb/s. System integration in a Liquid-Crystal-polymer (LCP) substrate is investigated. The integration of a tunable UWB-IR transmitter and a power scavenging unit are studied. Our contribution includes embedding and modeling the RF components and antenna in substrate and co-optimizing the chip and package with on-chip versus off-chip passives trade-offs. Simulation results verify the potential of system-on-package solution for UWB integration. The effect of antenna miniaturization in a UWB system is studied. Our focus is to scale down a UWB antenna and optimize the performance through the chip-antenna co-design. A tunable impulse- UWB transmitter is designed in two cases - a conventional 50Ω design and a co-design methodology. The simulation results show that the standard 50Ω design technique can not reach the best condition in all cases, when a real antenna is placed into the system. The performance can be improved significantly when doing codesign. The antennas and UWB transmitter performances are evaluated in a given UWB systems. It is shown that the operation distance at a target performance is reduced with antenna scaling factor and it can be compensated by antenna-transceiver co-design. The result proves the importance of antenna-transceiver codesign, which needs to be addressed in the earliest phases of the design flow.

In this work, a 10 Mb/s impulse UWB RFID tag in 0.18 mum CMOS is presented. The tag is remotely powered by a UHF signal with a minimum input RF power as low as 14.1 muW. The primary innovation is to employ two different communication links (UWB and UHF) respectively in the uplink and downlink of the tag. This is because the amount of data or instructions from a reader to a tag is small and as a result a conventional UHF-RFID link at 900MHz can be used as the downlink. The UHF signal also provides remote power to the tag. The uplink requires higher data rates and precise positioning capability therefore an l-UWB transmitter is employed.

In this paper, we describe an impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications. Different architectures have been studied for base station and sensor nodes. The base station node uses coherent UWB architecture because of the high performance and good sensitivity requirements. However, to meet complexity, power and cost constraints, the sensor module uses a novel non-coherent architecture that can autonomously detect the UWB signals. The radio modules include a transceiver block, a baseband processing unit and a power management block. The transceiver block includes a Gaussian pulse generator, a multiplier, an integrator and timing circuits. For long range applications, a wideband low noise amplifier (LNA) is included in the transceiver of the sensor module, whereas in short range applications it is simply eliminated to further reduce the power consumption. In order to verify the proposed system concept, circuit level implementation is studied using 1.5 V 0.18 mu m CMOS technology. Finally, the UWB radio modules have been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SOP) technology for low power, low cost and small size integration. A small low cost, double-slotted, Knight's helm antenna is embedded in the LCP substrate, which shows stable characterization and a return loss better than -10 dB over the UWB band.

In this paper we present a self-powered CMOS ultra wideband radio transmitter integrated in a Liquid-Crystal Polymer (LCP) based System on Package (SoP) module with an embedded small antenna. Chip-package-antenna co-design is performed for this module in the presence of unwanted packaging parasitic effects and optimizes the transmission efficiency. Our contribution includes new modeling of the RF-package and antenna and co-optimizing the chip and package design with on-chip versus off-chip passives trade-offs. The Sop module consists of an innovative tunable low power CMOS transmitter for IR-UWB communication, a double-slotted small-size embedded UWB antenna, and a power converter. The output amplitude and duration of the transmitter can be tuned to transmit a signal meeting the FCC mask in different pulse repetition rate for long and short range applications. This ability can also be used to compensate the process and temperature variations as well as the parasitic effects of packaging and antenna. The antenna has a return loss of better than -10dB. The power converter consists of a chain of surface mounted shottkey diodes and capacitors, which converts incident electromagnetic waves to DC supply and thus power up the transmitter. The final module is implemented in LCP substrate with integrated passive components and embedded antenna. The chip part is implemented in 0.18um CMOS process.

In this paper, the benefit of a co-design between a modified small-size Printed Tapered Monopole Antenna (PTMA) and an Impulse Ultra Wideband transmitter Is Investigated for the 3.1-10.6GHz bond. A comparison is given between a 50 Omega design and a co-designed version. The simulation results show that with the co-design method the tunable UWB transmitter can reach the bandwidth regulation for a much smaller antenna.

Ultra wideband radio is an emerging wireless standard that uses sub-nanosecond pulses to transmit data, resulting in several GHz bandwidths. The problem of generating a synchronized template respect to the received signal grows in complexity as the signal bandwidth increases. In this paper, an innovative, low cost, non-coherent receiver architecture is proposed for autonomous detection of ultra wideband signals. The new receiver will self-generate a synchronous template and hence, no transmitter-reference synchronizer is required. We validate its performance via simulations compared with coherent receivers and conventional non-coherent receivers, the new architecture is found much more robust to timing noise and hence greatly facilitates the synchronise problem in UWB receiver.

In this paper, we present a novel passive CMOS module which uses two different standards in uplink and downlink. It can be used in many applications such as Radio Frequency Identification (RFID), and ubiquitous wireless sensing. Such as conventional RFID systems, the module captures power supply from received RF signal transmitted by a reader and extracts data and clock by using an envelope detector and PIE encoder. However, in uplink instead of back scattering, an Impulse-UWB transmitter is used to improve the system performance and throughput. The UWB communication offers several advantages to the system. A new communication protocol is proposed for the system based on slotted-ALOHA anti-collision algorithm. The module consisting of a power management unit, an RF narrowband receiver, a clock management unit, an IR-UWB transmitter, and a digital baseband are designed in 0.18 CMOS process.

In this paper, we present a radio-powered module with asymmetric wireless link utilizing ultra wideband radio system for RFID and wireless sensor applications. Our contribution includes using two different standards in uplink and downlink. Such as conventional RFIDs, incoming RF signal transmitted by reader is used to power the internal circuitry and receive the data. However, in upstream link, an IR-UWB transmitter is utilized. Unlike traditional RFID systems, due to great advantages of UWB communication, this tag is very robust to multi-path fading and collision problem and it is more secure against eavesdropping or jamming. The module consists of a power scavenging unit, a RF receiver, an IR-UWB transmitter, digital baseband controller, and an embedded UWB antenna are designed for integration on Liquid-Crystal Polymer (LCP) substrate, using 0.18um CMOS process technology.

In this paper we present a power management and a clock generator for a novel passive UWB tag. It can be used in many applications such as Radio Frequency Identification (RFID), and ubiquitous wireless sensing. As same as conventional RFID, the tag captures the power from the incoming RF signal, converts to DC and stores it in a relatively big capacitor. A voltage sensor and a regulator provide stable voltage for the whole circuitry during operation mode. A clock circuitry generates a low jitter and low skew clock for ultra wideband transmitter to transmit data. In such passive system the power consumption of each block should be as low as possible. On the other hand, performance degradation across process, voltage, and temperature variation (PVT) is another problematic challenge in low power and low cost circuit implementation. In this work, the power management unit including of an RF power scavenging, a voltage sensor, a low drop out regulator and a clock generator are designed and their performance across PVT variation are analyzed. The module is designed and is fabricated in CMOS 0.18 mu m technology.

Communication networks have evolved from circuit-switched and hop-by-hop routed systems into hybrid data/optical networks using the Internet as a common backbone carrying narrow- and broad-band traffic offered by a multitude of access networks. This data/optical backbone is built around a multi-technology/multi-protocol routing architecture which runs the IP protocols in a collapsed IP stack where ATM and SONET/SDH have been replaced by the suite of Generalized Multiprotocol Label Switching (GMPLS) protocols. A further evolution referred to as ``IP over Photons'' or ``All IP - All Optical'' is expected where ``redundant intermediate layers'' will be eliminated to run IP directly on top of optical cross-connects (OXCs) with the expectation of achieving savings on operation expenditures (OPEX) and capital expenditures (CAPEX). ``IP over Photons'' has been stalled by the immaturity in the control and data plane technologies leading to complex and time-consuming manual network planning and configurations which require a group of ``layer experts'' to operate and maintain a hybrid data/optical network.

By making the status of each link and node of a data/optical network visible to a common control, GMPLS protocols have opened the way for automated operation and management allowing the different layers of an IP stack to be managed by a single network operator. GMPLS protocols provide the potential to make more efficient use of the IP backbone by having network management techniques such as Traffic Engineering (TE) and Network Engineering (NE), once the preserve of telecommunications, to be reinvented and deployed to effect different Quality of Service (QoS) requirements in the IP networks. NE moves bandwidth to where the traffic is offered to the network while TE moves traffic to where the bandwidth is available to achieve QoS agreements between the current and expected traffic and the available resources. However,several issues need to be resolved before TE and NE be effectively deployed in emerging and next generation IP networks. These include (1) the identification of QoS requirements of the different network layer interfaces of the emerging and next generation IP stack (2) the mapping of these QoS requirements into QoS routing mechanisms and network control strategies and (3) the deployment of these mechanisms and strategies within and beyond an Internet domain's boundaries to maximize the engineering and economic efficiency.

Building upon different frameworks and research fields, this thesis revisits the issue of Traffic and Network Engineering (TE and NE) to present and evaluate the performance of different QoS routing mechanisms and network control strategies when deployed at different network layer interfaces of a hybrid data/optical network where an IP over MPLS network is layered above an MP λS/Fiber infrastructure. These include mechanisms and strategies to be deployed at the IP/MPLS, MPLS/MP λS and MP λS/Fiber network layer interfaces. The main contributions of this thesis are threefold. First we propose and compare the performance of hybrid routing approaches to be deployed in IP/MPLS networks by combining connectionless routing mechanisms used by classical IGP protocols and the connection oriented routing approach borrowed from MPLS. Second, we present QoS routing mechanisms and network control strategies to be deployed at the MPLS/MP λS network layer interface with a focus on contention-aware routing and inter-layer visibility to improve multi-layer optimality and resilience. Finally, we build upon fiber transmission characteristics to propose QoS routing mechanisms where the routing in the MPLS and MP λS layers is conducted by Photonic characteristics of the fiber such as the availability of the physical link and its failure risk group probability.

This paper presents a new approach for routing flows in IP networks. The approach referred to as the <I>Least Path Interference (LPI)</I> is based on a route optimisation model which (1) moves the traffic away from path interfering links (the path interference quantifying the network reliability) to re-route fewer flows upon link failure and (2) maximises the link congestion distance (quantifying the network optimality) to reject fewer flows under congestion. LPI implements a hybrid traffic engineering model combining offline estimation of the path interference and online path selection. LPI is based on a simple path selection model where no changes to the traditional routing algorithms are required besides designing a new mixed cost metric to combine reliability and optimality. The Least Path Interfering Algorithm (LPIA ); a routing algorithm derived from LPI is applied to compute paths for the traffic offered to a 20- and 50-node networks. Simulation reveals (1) performance improvements compared to Open Shortest Path First (OSPF) and Constraint Shortest Path First (CSPF) routing in terms of routing optimality and network reliability and (2) the same performance as the recently proposed Least Interference Optimisation Algorithm (LIOA) algorithm with less signalling overheads.

We present a new Traffic engineering (TE) model which is based on QoS rerouting and uses hybrid resilience to improve the recovery performance of multi-layer networks where an MPLS network is layered above an MP lambda S network. We formulate the rerouting of the LSPs/lambda SPs as a multi-constrained problem and use its polynomial reduction to find a heuristic solution that can be implemented by standardized constraint-based routing algorithms. This heuristic solution uses a cost-based routing optimization to achieve different network configurations which multiplex/separate bandwidth-aware LSPs/lambda SPs on the network links. We formulate the resilience upon failure as a multi-objective problem consisting of finding a resilience strategy that minimizes recovery operation time and maximizes the LSP/lambda SP restorability. A solution to this problem is proposed where a hybrid resilience framework is used to achieve restoration in the MPLS layer to complement path switching in the MP lambda S layer. We evaluate the performance of the TE model when rerouting the tunnels carrying the traffic offered to a 23- and 31-node networks. Simulation reveals that the hybrid resilience model performs better than classical recovery mechanisms in terms of restorability, quality of rerouting paths and rerouting; stability.

We revisit the concept of path multiplexing/separation and its impact on the recovery performance in converged data/optical networks. We formulate the rerouting of failed tunnels as a path set finding problem subject to quality of service (QoS) and network control constraints. We solve this problem using a heuristic solution that is based on a cost metric that (1) uses congestion in the optical layer to guide routing decisions and (2) engineers converged multiprotocol label switching networks and multiprotocol lambda switching (MPLS/MPλ S) networks to achieve path multiplexing/separation when rerouting the label switched paths (LSPs) and the lambda switched paths (λ SPs). We apply this solution to achieve multilayer resilience using a mixed scheme where protection switching is complemented by path restoration. We evaluate the performance of this scheme when rerouting the tunnels carrying the traffic offered to 15- and 23-node networks. Simulation reveals performance improvements of the proposed scheme when compared with classical recovery schemes that use several other existing algorithms such as minimum hop algorithm (MHA), open shortest path first (OSPF), and widest shortest path (WSP) in terms of the rerouting efficiency and bandwidth usage optimization.

this paper presents a CMOS voltage controlled oscillator for multi standard wireless transceivers. The VCO structure is based on All- PMOS LC oscillators. The frequency range extends from 1.7 GHz to 2.5 GH, and tuning between frequencies is done by means of capacitor banks and varactors.

Distributed programming is usually considered both difficult and inherently different from concurrent centralized programming. It is thought that the distributed programming systems that we ultimately deploy, in the future, when we've worked out all the details, will require a very different programming model and will even need to be evaluated by new criteria.

The Mozart Programming System, described in this thesis, demonstrates that this need not be the case. It is shown that, with a good system design, distributed programming can be seen as an extended form of concurrent programming. This is from the programmer's point-of-view; under the hood the design and implementation will necessarily be more complex. We relate the Mozart system with the classical transparencies of distributed systems. We show that some of these are inherently on the application level, while as Mozart demonstrates, others can and should be dealt with on the language/system level.

The extensions to the programming model, given the right concurrent programming base, are mainly concerned with non-functional properties of programs. The models and tuning facilities for failure and performance need to take latency, bandwidth, and partial failure into account. Other than that there need not be any difference between concurrent programming and distributed programming.

The Mozart Programming System is based on the concurrent programming language Oz, which integrates, in a coherent way, all three known concurrency or thread-interaction models. These are message-passing (like Erlang), shared objects (like Java with threads) and shared data-flow variables. The Mozart design philosophy is thus applicable over the entire range of concurrent programming languages/systems. We have extracted from the experience with Mozart a number of principles and properties that are applicable to the design and implementation of all (general-purpose) distributed programming systems.

The full range of the design and implementation issues behind Mozart are presented. This includes a description of the consistency protocols that make transparency possible for the full language, including distributed objects and distributed data-flow variables.

Mozart is extensively compared with other approaches to distributed programming, in general, and to other language-based distributed programming systems, in particular

We combine and extend recent results in autonomic computing and structuredpeer-to-peer to build an infrastructure for constructing and managing dynamic vir-tual organizations. The paper focuses on the middle layer of the proposed infras-tructure, in-between the Niche overlay system on the bottom, and an architecture-based management system based on Jade on the top.  The middle layer, theoverlay services, are responsible for all sensing and actuation carried out by theVO management. We describe in detail the API of the resource and componentoverlay services both on the management node and the nodes hosting resources.We present a simple use case demonstrating resource discovery, initial deploy-ment, self-configuration as a result of resource availability change, self-healing,self-tuning and self-protection. The advantages of the design are 1) the overlayservices are in themselves self-managing, and sensor/actuation services they pro-vide are robust, 2) management can be dealt with declaratively and at a high-level,and 3) the overlay services provide good scalability in dynamic VOs.

The project will address two main challenges of prevailing architectures: 1) The global Interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; 2) The difficulties in programming heterogeneous, multi-core platforms, in particular in dynamically managing data structures in distributed memory. MOSART aims to overcome these through a multi-core architecture with distributed memory organisation, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimised and customised together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: A) Providing platform support for management of abstract data structures Including middleware services and a run-time data manager for NoC based communication infrastructure; 2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.

With the ever increasing importance of social net- working sites and services, socially intelligent agents who are responsible for gathering, managing and maintaining knowledge surrounding individual users are of increasing interest to both computing research communities as well as industries. For these agents to be able to fully capture and manage the knowledge about a user’s interaction with these social sites and services, a social user model needs to be introduced. A social user model is defined as a generic user model (model capable of capturing generic information related to a user), plus social dimensions of users (models capturing social aspects of user such as activities and social contexts). While existing models capture a proportion of such information, they fail to model and present ones of the most important dimensions of social connectivity: trust and privacy. To this end, in this paper, we introduce an ontological model of social user, composed by a generic user model component, which imports existing well-known user model structures, a social model, which contains social dimensions, and trust, reputation and privacy become the pivotal concepts gluing the whole ontological knowledge models together.

This paper is an investigation of off-chip solution of power converters for passive UHF RFID transponders. The power converter, consisting of a chain of schottky diodes and capacitors, is designed and then implemented on Rogers4350 PCB substrate. The ISM unlicensed frequency bands 915 MHz is used for RF signal. The measurement results show that with minimum input power of -4.7dBm, the power converter achieves 1.8V/ 5 mu A output driving capability, which is sufficient for the transponder operation. It corresponds to a 3.6m operating distance when 4-W EIRP radiation is allowed.

This paper is an investigation of off-chip solution of power converters for passive UHF RFID transponders. The power converter, consisting of a chain of schottky diodes and capacitors, is designed and then implemented on Rogers4350 PCB substrate. The ISM unlicensed frequency bands 915 MHz is used for RF signal. The deembedded measurement results show that with minimum input power of -4.7dBm, the power converter achieves 1.8V/5 mu A output driving capability, which is sufficient for the transponder operation. It corresponds to a 3.6m operating distance when 4-W EIRP radiation is allowed.

Since previous publications show conflicting results about sizing device, relationship between device size and 1/f(2) phase noise is studied and closed-form equations are derived in order to help designers to size devices in LC-tank oscillators for good phase noise performance. The analysis is divided into two steps. Firstly, periodic noise transfer functions of each VCO noise source to the output of switch FETs are derived, and the impact of sizing on these functions is discussed. Secondly, phase noise equations are derived with these functions. Experiments show that phase noise predicted by the equations agrees with that from simulations.